AT91SAM7S256.h
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00055 #ifndef AT91SAM7S256_H
00056 #define AT91SAM7S256_H
00057
00058 #ifndef __ASSEMBLY__
00059 typedef volatile unsigned int AT91_REG;
00060 #define AT91_CAST(a) (a)
00061 #else
00062 #define AT91_CAST(a)
00063 #endif
00064
00065
00066
00067
00068 #ifndef __ASSEMBLY__
00069 typedef struct _AT91S_SYS {
00070 AT91_REG AIC_SMR[32];
00071 AT91_REG AIC_SVR[32];
00072 AT91_REG AIC_IVR;
00073 AT91_REG AIC_FVR;
00074 AT91_REG AIC_ISR;
00075 AT91_REG AIC_IPR;
00076 AT91_REG AIC_IMR;
00077 AT91_REG AIC_CISR;
00078 AT91_REG Reserved0[2];
00079 AT91_REG AIC_IECR;
00080 AT91_REG AIC_IDCR;
00081 AT91_REG AIC_ICCR;
00082 AT91_REG AIC_ISCR;
00083 AT91_REG AIC_EOICR;
00084 AT91_REG AIC_SPU;
00085 AT91_REG AIC_DCR;
00086 AT91_REG Reserved1[1];
00087 AT91_REG AIC_FFER;
00088 AT91_REG AIC_FFDR;
00089 AT91_REG AIC_FFSR;
00090 AT91_REG Reserved2[45];
00091 AT91_REG DBGU_CR;
00092 AT91_REG DBGU_MR;
00093 AT91_REG DBGU_IER;
00094 AT91_REG DBGU_IDR;
00095 AT91_REG DBGU_IMR;
00096 AT91_REG DBGU_CSR;
00097 AT91_REG DBGU_RHR;
00098 AT91_REG DBGU_THR;
00099 AT91_REG DBGU_BRGR;
00100 AT91_REG Reserved3[7];
00101 AT91_REG DBGU_CIDR;
00102 AT91_REG DBGU_EXID;
00103 AT91_REG DBGU_FNTR;
00104 AT91_REG Reserved4[45];
00105 AT91_REG DBGU_RPR;
00106 AT91_REG DBGU_RCR;
00107 AT91_REG DBGU_TPR;
00108 AT91_REG DBGU_TCR;
00109 AT91_REG DBGU_RNPR;
00110 AT91_REG DBGU_RNCR;
00111 AT91_REG DBGU_TNPR;
00112 AT91_REG DBGU_TNCR;
00113 AT91_REG DBGU_PTCR;
00114 AT91_REG DBGU_PTSR;
00115 AT91_REG Reserved5[54];
00116 AT91_REG PIOA_PER;
00117 AT91_REG PIOA_PDR;
00118 AT91_REG PIOA_PSR;
00119 AT91_REG Reserved6[1];
00120 AT91_REG PIOA_OER;
00121 AT91_REG PIOA_ODR;
00122 AT91_REG PIOA_OSR;
00123 AT91_REG Reserved7[1];
00124 AT91_REG PIOA_IFER;
00125 AT91_REG PIOA_IFDR;
00126 AT91_REG PIOA_IFSR;
00127 AT91_REG Reserved8[1];
00128 AT91_REG PIOA_SODR;
00129 AT91_REG PIOA_CODR;
00130 AT91_REG PIOA_ODSR;
00131 AT91_REG PIOA_PDSR;
00132 AT91_REG PIOA_IER;
00133 AT91_REG PIOA_IDR;
00134 AT91_REG PIOA_IMR;
00135 AT91_REG PIOA_ISR;
00136 AT91_REG PIOA_MDER;
00137 AT91_REG PIOA_MDDR;
00138 AT91_REG PIOA_MDSR;
00139 AT91_REG Reserved9[1];
00140 AT91_REG PIOA_PPUDR;
00141 AT91_REG PIOA_PPUER;
00142 AT91_REG PIOA_PPUSR;
00143 AT91_REG Reserved10[1];
00144 AT91_REG PIOA_ASR;
00145 AT91_REG PIOA_BSR;
00146 AT91_REG PIOA_ABSR;
00147 AT91_REG Reserved11[9];
00148 AT91_REG PIOA_OWER;
00149 AT91_REG PIOA_OWDR;
00150 AT91_REG PIOA_OWSR;
00151 AT91_REG Reserved12[469];
00152 AT91_REG PMC_SCER;
00153 AT91_REG PMC_SCDR;
00154 AT91_REG PMC_SCSR;
00155 AT91_REG Reserved13[1];
00156 AT91_REG PMC_PCER;
00157 AT91_REG PMC_PCDR;
00158 AT91_REG PMC_PCSR;
00159 AT91_REG Reserved14[1];
00160 AT91_REG PMC_MOR;
00161 AT91_REG PMC_MCFR;
00162 AT91_REG Reserved15[1];
00163 AT91_REG PMC_PLLR;
00164 AT91_REG PMC_MCKR;
00165 AT91_REG Reserved16[3];
00166 AT91_REG PMC_PCKR[3];
00167 AT91_REG Reserved17[5];
00168 AT91_REG PMC_IER;
00169 AT91_REG PMC_IDR;
00170 AT91_REG PMC_SR;
00171 AT91_REG PMC_IMR;
00172 AT91_REG Reserved18[36];
00173 AT91_REG RSTC_RCR;
00174 AT91_REG RSTC_RSR;
00175 AT91_REG RSTC_RMR;
00176 AT91_REG Reserved19[5];
00177 AT91_REG RTTC_RTMR;
00178 AT91_REG RTTC_RTAR;
00179 AT91_REG RTTC_RTVR;
00180 AT91_REG RTTC_RTSR;
00181 AT91_REG PITC_PIMR;
00182 AT91_REG PITC_PISR;
00183 AT91_REG PITC_PIVR;
00184 AT91_REG PITC_PIIR;
00185 AT91_REG WDTC_WDCR;
00186 AT91_REG WDTC_WDMR;
00187 AT91_REG WDTC_WDSR;
00188 AT91_REG Reserved20[5];
00189 AT91_REG VREG_MR;
00190 } AT91S_SYS, *AT91PS_SYS;
00191 #else
00192
00193 #endif
00194
00195
00196
00197
00198 #ifndef __ASSEMBLY__
00199 typedef struct _AT91S_AIC {
00200 AT91_REG AIC_SMR[32];
00201 AT91_REG AIC_SVR[32];
00202 AT91_REG AIC_IVR;
00203 AT91_REG AIC_FVR;
00204 AT91_REG AIC_ISR;
00205 AT91_REG AIC_IPR;
00206 AT91_REG AIC_IMR;
00207 AT91_REG AIC_CISR;
00208 AT91_REG Reserved0[2];
00209 AT91_REG AIC_IECR;
00210 AT91_REG AIC_IDCR;
00211 AT91_REG AIC_ICCR;
00212 AT91_REG AIC_ISCR;
00213 AT91_REG AIC_EOICR;
00214 AT91_REG AIC_SPU;
00215 AT91_REG AIC_DCR;
00216 AT91_REG Reserved1[1];
00217 AT91_REG AIC_FFER;
00218 AT91_REG AIC_FFDR;
00219 AT91_REG AIC_FFSR;
00220 } AT91S_AIC, *AT91PS_AIC;
00221 #else
00222 #define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
00223 #define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
00224 #define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
00225 #define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
00226 #define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
00227 #define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
00228 #define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
00229 #define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
00230 #define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
00231 #define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
00232 #define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
00233 #define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
00234 #define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
00235 #define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
00236 #define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
00237 #define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
00238 #define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
00239 #define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
00240
00241 #endif
00242
00243 #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
00244 #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
00245 #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
00246 #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
00247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
00248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
00249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
00250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
00251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
00252 #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
00253
00254 #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
00255 #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
00256
00257 #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
00258 #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
00259
00260
00261
00262
00263 #ifndef __ASSEMBLY__
00264 typedef struct _AT91S_PDC {
00265 AT91_REG PDC_RPR;
00266 AT91_REG PDC_RCR;
00267 AT91_REG PDC_TPR;
00268 AT91_REG PDC_TCR;
00269 AT91_REG PDC_RNPR;
00270 AT91_REG PDC_RNCR;
00271 AT91_REG PDC_TNPR;
00272 AT91_REG PDC_TNCR;
00273 AT91_REG PDC_PTCR;
00274 AT91_REG PDC_PTSR;
00275 } AT91S_PDC, *AT91PS_PDC;
00276 #else
00277 #define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
00278 #define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
00279 #define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
00280 #define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
00281 #define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
00282 #define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
00283 #define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
00284 #define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
00285 #define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
00286 #define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
00287
00288 #endif
00289
00290 #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
00291 #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
00292 #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
00293 #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
00294
00295
00296
00297
00298
00299 #ifndef __ASSEMBLY__
00300 typedef struct _AT91S_DBGU {
00301 AT91_REG DBGU_CR;
00302 AT91_REG DBGU_MR;
00303 AT91_REG DBGU_IER;
00304 AT91_REG DBGU_IDR;
00305 AT91_REG DBGU_IMR;
00306 AT91_REG DBGU_CSR;
00307 AT91_REG DBGU_RHR;
00308 AT91_REG DBGU_THR;
00309 AT91_REG DBGU_BRGR;
00310 AT91_REG Reserved0[7];
00311 AT91_REG DBGU_CIDR;
00312 AT91_REG DBGU_EXID;
00313 AT91_REG DBGU_FNTR;
00314 AT91_REG Reserved1[45];
00315 AT91_REG DBGU_RPR;
00316 AT91_REG DBGU_RCR;
00317 AT91_REG DBGU_TPR;
00318 AT91_REG DBGU_TCR;
00319 AT91_REG DBGU_RNPR;
00320 AT91_REG DBGU_RNCR;
00321 AT91_REG DBGU_TNPR;
00322 AT91_REG DBGU_TNCR;
00323 AT91_REG DBGU_PTCR;
00324 AT91_REG DBGU_PTSR;
00325 } AT91S_DBGU, *AT91PS_DBGU;
00326 #else
00327 #define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
00328 #define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
00329 #define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
00330 #define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
00331 #define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
00332 #define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
00333 #define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
00334 #define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
00335 #define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
00336 #define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
00337 #define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
00338 #define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
00339
00340 #endif
00341
00342 #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
00343 #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
00344 #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
00345 #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
00346 #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
00347 #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
00348 #define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
00349
00350 #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
00351 #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
00352 #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
00353 #define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
00354 #define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
00355 #define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
00356 #define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
00357 #define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
00358 #define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
00359 #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
00360 #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
00361 #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
00362
00363 #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
00364 #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
00365 #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
00366 #define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
00367 #define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
00368 #define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
00369 #define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
00370 #define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
00371 #define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
00372 #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
00373 #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
00374 #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
00375
00376
00377
00378
00379 #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
00380
00381
00382
00383
00384 #ifndef __ASSEMBLY__
00385 typedef struct _AT91S_PIO {
00386 AT91_REG PIO_PER;
00387 AT91_REG PIO_PDR;
00388 AT91_REG PIO_PSR;
00389 AT91_REG Reserved0[1];
00390 AT91_REG PIO_OER;
00391 AT91_REG PIO_ODR;
00392 AT91_REG PIO_OSR;
00393 AT91_REG Reserved1[1];
00394 AT91_REG PIO_IFER;
00395 AT91_REG PIO_IFDR;
00396 AT91_REG PIO_IFSR;
00397 AT91_REG Reserved2[1];
00398 AT91_REG PIO_SODR;
00399 AT91_REG PIO_CODR;
00400 AT91_REG PIO_ODSR;
00401 AT91_REG PIO_PDSR;
00402 AT91_REG PIO_IER;
00403 AT91_REG PIO_IDR;
00404 AT91_REG PIO_IMR;
00405 AT91_REG PIO_ISR;
00406 AT91_REG PIO_MDER;
00407 AT91_REG PIO_MDDR;
00408 AT91_REG PIO_MDSR;
00409 AT91_REG Reserved3[1];
00410 AT91_REG PIO_PPUDR;
00411 AT91_REG PIO_PPUER;
00412 AT91_REG PIO_PPUSR;
00413 AT91_REG Reserved4[1];
00414 AT91_REG PIO_ASR;
00415 AT91_REG PIO_BSR;
00416 AT91_REG PIO_ABSR;
00417 AT91_REG Reserved5[9];
00418 AT91_REG PIO_OWER;
00419 AT91_REG PIO_OWDR;
00420 AT91_REG PIO_OWSR;
00421 } AT91S_PIO, *AT91PS_PIO;
00422 #else
00423 #define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
00424 #define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
00425 #define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
00426 #define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
00427 #define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
00428 #define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
00429 #define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
00430 #define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
00431 #define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
00432 #define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
00433 #define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
00434 #define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
00435 #define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
00436 #define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
00437 #define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
00438 #define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
00439 #define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
00440 #define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
00441 #define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
00442 #define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
00443 #define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
00444 #define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
00445 #define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
00446 #define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
00447 #define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
00448 #define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
00449 #define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
00450 #define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
00451 #define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
00452
00453 #endif
00454
00455
00456
00457
00458 #ifndef __ASSEMBLY__
00459 typedef struct _AT91S_CKGR {
00460 AT91_REG CKGR_MOR;
00461 AT91_REG CKGR_MCFR;
00462 AT91_REG Reserved0[1];
00463 AT91_REG CKGR_PLLR;
00464 } AT91S_CKGR, *AT91PS_CKGR;
00465 #else
00466 #define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
00467 #define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
00468 #define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
00469
00470 #endif
00471
00472 #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
00473 #define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
00474 #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
00475
00476 #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
00477 #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
00478
00479 #define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
00480 #define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
00481 #define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
00482 #define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
00483 #define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
00484 #define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
00485 #define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
00486 #define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
00487 #define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
00488 #define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
00489 #define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
00490 #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
00491 #define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
00492 #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
00493
00494
00495
00496
00497 #ifndef __ASSEMBLY__
00498 typedef struct _AT91S_PMC {
00499 AT91_REG PMC_SCER;
00500 AT91_REG PMC_SCDR;
00501 AT91_REG PMC_SCSR;
00502 AT91_REG Reserved0[1];
00503 AT91_REG PMC_PCER;
00504 AT91_REG PMC_PCDR;
00505 AT91_REG PMC_PCSR;
00506 AT91_REG Reserved1[1];
00507 AT91_REG PMC_MOR;
00508 AT91_REG PMC_MCFR;
00509 AT91_REG Reserved2[1];
00510 AT91_REG PMC_PLLR;
00511 AT91_REG PMC_MCKR;
00512 AT91_REG Reserved3[3];
00513 AT91_REG PMC_PCKR[3];
00514 AT91_REG Reserved4[5];
00515 AT91_REG PMC_IER;
00516 AT91_REG PMC_IDR;
00517 AT91_REG PMC_SR;
00518 AT91_REG PMC_IMR;
00519 } AT91S_PMC, *AT91PS_PMC;
00520 #else
00521 #define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
00522 #define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
00523 #define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
00524 #define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
00525 #define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
00526 #define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
00527 #define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
00528 #define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
00529 #define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
00530 #define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
00531 #define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
00532 #define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
00533
00534 #endif
00535
00536 #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
00537 #define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
00538 #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
00539 #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
00540 #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
00541
00542
00543
00544
00545
00546
00547 #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
00548 #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
00549 #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
00550 #define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
00551 #define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
00552 #define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
00553 #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
00554 #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
00555 #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
00556 #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
00557 #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
00558 #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
00559
00560
00561 #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
00562 #define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
00563 #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
00564 #define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
00565 #define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
00566 #define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
00567
00568
00569
00570
00571
00572
00573
00574 #ifndef __ASSEMBLY__
00575 typedef struct _AT91S_RSTC {
00576 AT91_REG RSTC_RCR;
00577 AT91_REG RSTC_RSR;
00578 AT91_REG RSTC_RMR;
00579 } AT91S_RSTC, *AT91PS_RSTC;
00580 #else
00581 #define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
00582 #define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
00583 #define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
00584
00585 #endif
00586
00587 #define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
00588 #define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
00589 #define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
00590 #define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
00591
00592 #define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
00593 #define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
00594 #define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
00595 #define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
00596 #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
00597 #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
00598 #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
00599 #define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
00600 #define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
00601 #define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
00602 #define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
00603
00604 #define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
00605 #define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
00606 #define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
00607 #define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
00608
00609
00610
00611
00612 #ifndef __ASSEMBLY__
00613 typedef struct _AT91S_RTTC {
00614 AT91_REG RTTC_RTMR;
00615 AT91_REG RTTC_RTAR;
00616 AT91_REG RTTC_RTVR;
00617 AT91_REG RTTC_RTSR;
00618 } AT91S_RTTC, *AT91PS_RTTC;
00619 #else
00620 #define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
00621 #define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
00622 #define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
00623 #define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
00624
00625 #endif
00626
00627 #define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
00628 #define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
00629 #define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
00630 #define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
00631
00632 #define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
00633
00634 #define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
00635
00636 #define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
00637 #define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
00638
00639
00640
00641
00642 #ifndef __ASSEMBLY__
00643 typedef struct _AT91S_PITC {
00644 AT91_REG PITC_PIMR;
00645 AT91_REG PITC_PISR;
00646 AT91_REG PITC_PIVR;
00647 AT91_REG PITC_PIIR;
00648 } AT91S_PITC, *AT91PS_PITC;
00649 #else
00650 #define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
00651 #define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
00652 #define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
00653 #define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
00654
00655 #endif
00656
00657 #define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
00658 #define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
00659 #define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
00660
00661 #define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
00662
00663 #define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
00664 #define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
00665
00666
00667
00668
00669
00670 #ifndef __ASSEMBLY__
00671 typedef struct _AT91S_WDTC {
00672 AT91_REG WDTC_WDCR;
00673 AT91_REG WDTC_WDMR;
00674 AT91_REG WDTC_WDSR;
00675 } AT91S_WDTC, *AT91PS_WDTC;
00676 #else
00677 #define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
00678 #define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
00679 #define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
00680
00681 #endif
00682
00683 #define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
00684 #define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
00685
00686 #define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
00687 #define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
00688 #define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
00689 #define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
00690 #define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
00691 #define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
00692 #define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
00693 #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
00694
00695 #define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
00696 #define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
00697
00698
00699
00700
00701 #ifndef __ASSEMBLY__
00702 typedef struct _AT91S_VREG {
00703 AT91_REG VREG_MR;
00704 } AT91S_VREG, *AT91PS_VREG;
00705 #else
00706 #define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
00707
00708 #endif
00709
00710 #define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
00711
00712
00713
00714
00715 #ifndef __ASSEMBLY__
00716 typedef struct _AT91S_MC {
00717 AT91_REG MC_RCR;
00718 AT91_REG MC_ASR;
00719 AT91_REG MC_AASR;
00720 AT91_REG Reserved0[21];
00721 AT91_REG MC_FMR;
00722 AT91_REG MC_FCR;
00723 AT91_REG MC_FSR;
00724 } AT91S_MC, *AT91PS_MC;
00725 #else
00726 #define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
00727 #define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
00728 #define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
00729 #define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
00730 #define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
00731 #define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
00732
00733 #endif
00734
00735 #define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
00736
00737 #define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
00738 #define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
00739 #define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
00740 #define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
00741 #define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
00742 #define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
00743 #define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
00744 #define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
00745 #define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
00746 #define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
00747 #define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
00748 #define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
00749 #define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
00750 #define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
00751
00752 #define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
00753 #define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
00754 #define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
00755 #define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
00756 #define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
00757 #define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
00758 #define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
00759 #define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
00760 #define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
00761 #define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
00762
00763 #define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
00764 #define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
00765 #define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
00766 #define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
00767 #define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
00768 #define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
00769 #define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
00770 #define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
00771 #define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
00772 #define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
00773 #define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
00774
00775 #define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
00776 #define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
00777 #define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
00778 #define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
00779 #define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
00780 #define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
00781 #define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
00782 #define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
00783 #define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
00784 #define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
00785 #define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
00786 #define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
00787 #define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
00788 #define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
00789 #define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
00790 #define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
00791 #define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
00792 #define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
00793 #define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
00794 #define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
00795 #define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
00796 #define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
00797 #define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
00798 #define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
00799 #define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
00800
00801
00802
00803
00804 #ifndef __ASSEMBLY__
00805 typedef struct _AT91S_SPI {
00806 AT91_REG SPI_CR;
00807 AT91_REG SPI_MR;
00808 AT91_REG SPI_RDR;
00809 AT91_REG SPI_TDR;
00810 AT91_REG SPI_SR;
00811 AT91_REG SPI_IER;
00812 AT91_REG SPI_IDR;
00813 AT91_REG SPI_IMR;
00814 AT91_REG Reserved0[4];
00815 AT91_REG SPI_CSR[4];
00816 AT91_REG Reserved1[48];
00817 AT91_REG SPI_RPR;
00818 AT91_REG SPI_RCR;
00819 AT91_REG SPI_TPR;
00820 AT91_REG SPI_TCR;
00821 AT91_REG SPI_RNPR;
00822 AT91_REG SPI_RNCR;
00823 AT91_REG SPI_TNPR;
00824 AT91_REG SPI_TNCR;
00825 AT91_REG SPI_PTCR;
00826 AT91_REG SPI_PTSR;
00827 } AT91S_SPI, *AT91PS_SPI;
00828 #else
00829 #define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
00830 #define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
00831 #define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
00832 #define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
00833 #define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
00834 #define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
00835 #define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
00836 #define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
00837 #define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
00838
00839 #endif
00840
00841 #define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
00842 #define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
00843 #define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
00844 #define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
00845
00846 #define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
00847 #define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
00848 #define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
00849 #define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
00850 #define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
00851 #define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
00852 #define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
00853 #define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
00854 #define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
00855 #define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
00856
00857 #define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
00858 #define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
00859
00860 #define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
00861 #define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
00862
00863 #define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
00864 #define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
00865 #define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
00866 #define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
00867 #define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
00868 #define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
00869 #define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
00870 #define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
00871 #define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
00872 #define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
00873 #define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
00874
00875
00876
00877
00878 #define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
00879 #define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
00880 #define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
00881 #define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
00882 #define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
00883 #define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
00884 #define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
00885 #define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
00886 #define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
00887 #define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
00888 #define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
00889 #define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
00890 #define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
00891 #define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
00892 #define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
00893 #define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
00894
00895
00896
00897
00898 #ifndef __ASSEMBLY__
00899 typedef struct _AT91S_ADC {
00900 AT91_REG ADC_CR;
00901 AT91_REG ADC_MR;
00902 AT91_REG Reserved0[2];
00903 AT91_REG ADC_CHER;
00904 AT91_REG ADC_CHDR;
00905 AT91_REG ADC_CHSR;
00906 AT91_REG ADC_SR;
00907 AT91_REG ADC_LCDR;
00908 AT91_REG ADC_IER;
00909 AT91_REG ADC_IDR;
00910 AT91_REG ADC_IMR;
00911 AT91_REG ADC_CDR0;
00912 AT91_REG ADC_CDR1;
00913 AT91_REG ADC_CDR2;
00914 AT91_REG ADC_CDR3;
00915 AT91_REG ADC_CDR4;
00916 AT91_REG ADC_CDR5;
00917 AT91_REG ADC_CDR6;
00918 AT91_REG ADC_CDR7;
00919 AT91_REG Reserved1[44];
00920 AT91_REG ADC_RPR;
00921 AT91_REG ADC_RCR;
00922 AT91_REG ADC_TPR;
00923 AT91_REG ADC_TCR;
00924 AT91_REG ADC_RNPR;
00925 AT91_REG ADC_RNCR;
00926 AT91_REG ADC_TNPR;
00927 AT91_REG ADC_TNCR;
00928 AT91_REG ADC_PTCR;
00929 AT91_REG ADC_PTSR;
00930 } AT91S_ADC, *AT91PS_ADC;
00931 #else
00932 #define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
00933 #define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
00934 #define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
00935 #define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
00936 #define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
00937 #define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
00938 #define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
00939 #define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
00940 #define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
00941 #define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
00942 #define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
00943 #define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
00944 #define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
00945 #define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
00946 #define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
00947 #define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
00948 #define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
00949 #define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
00950
00951 #endif
00952
00953 #define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
00954 #define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
00955
00956 #define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
00957 #define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
00958 #define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
00959 #define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
00960 #define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
00961 #define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
00962 #define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
00963 #define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
00964 #define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
00965 #define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
00966 #define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
00967 #define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
00968 #define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
00969 #define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
00970 #define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
00971 #define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
00972 #define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
00973 #define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
00974 #define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
00975 #define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
00976
00977 #define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
00978 #define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
00979 #define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
00980 #define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
00981 #define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
00982 #define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
00983 #define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
00984 #define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
00985
00986
00987
00988 #define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
00989 #define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
00990 #define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
00991 #define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
00992 #define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
00993 #define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
00994 #define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
00995 #define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
00996 #define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
00997 #define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
00998 #define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
00999 #define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
01000 #define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
01001 #define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
01002 #define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
01003 #define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
01004 #define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
01005 #define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
01006 #define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
01007 #define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
01008
01009 #define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
01010
01011
01012
01013
01014 #define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
01015
01016
01017
01018
01019
01020
01021
01022
01023
01024
01025
01026 #ifndef __ASSEMBLY__
01027 typedef struct _AT91S_SSC {
01028 AT91_REG SSC_CR;
01029 AT91_REG SSC_CMR;
01030 AT91_REG Reserved0[2];
01031 AT91_REG SSC_RCMR;
01032 AT91_REG SSC_RFMR;
01033 AT91_REG SSC_TCMR;
01034 AT91_REG SSC_TFMR;
01035 AT91_REG SSC_RHR;
01036 AT91_REG SSC_THR;
01037 AT91_REG Reserved1[2];
01038 AT91_REG SSC_RSHR;
01039 AT91_REG SSC_TSHR;
01040 AT91_REG Reserved2[2];
01041 AT91_REG SSC_SR;
01042 AT91_REG SSC_IER;
01043 AT91_REG SSC_IDR;
01044 AT91_REG SSC_IMR;
01045 AT91_REG Reserved3[44];
01046 AT91_REG SSC_RPR;
01047 AT91_REG SSC_RCR;
01048 AT91_REG SSC_TPR;
01049 AT91_REG SSC_TCR;
01050 AT91_REG SSC_RNPR;
01051 AT91_REG SSC_RNCR;
01052 AT91_REG SSC_TNPR;
01053 AT91_REG SSC_TNCR;
01054 AT91_REG SSC_PTCR;
01055 AT91_REG SSC_PTSR;
01056 } AT91S_SSC, *AT91PS_SSC;
01057 #else
01058 #define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
01059 #define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
01060 #define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
01061 #define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
01062 #define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
01063 #define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
01064 #define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
01065 #define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
01066 #define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
01067 #define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
01068 #define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
01069 #define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
01070 #define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
01071 #define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
01072
01073 #endif
01074
01075 #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
01076 #define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
01077 #define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
01078 #define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
01079 #define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
01080
01081 #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
01082 #define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
01083 #define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
01084 #define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
01085 #define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
01086 #define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
01087 #define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
01088 #define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
01089 #define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
01090 #define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
01091 #define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
01092 #define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
01093 #define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
01094 #define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
01095 #define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
01096 #define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
01097 #define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
01098 #define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
01099 #define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
01100 #define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
01101 #define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
01102
01103 #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
01104 #define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
01105 #define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
01106 #define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
01107 #define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
01108 #define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
01109 #define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
01110 #define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
01111 #define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
01112 #define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
01113 #define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
01114 #define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
01115 #define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
01116
01117
01118 #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
01119 #define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
01120
01121 #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
01122 #define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
01123 #define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
01124 #define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
01125 #define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
01126 #define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
01127 #define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
01128 #define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
01129 #define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
01130 #define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
01131 #define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
01132 #define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
01133
01134
01135
01136
01137
01138
01139
01140 #ifndef __ASSEMBLY__
01141 typedef struct _AT91S_USART {
01142 AT91_REG US_CR;
01143 AT91_REG US_MR;
01144 AT91_REG US_IER;
01145 AT91_REG US_IDR;
01146 AT91_REG US_IMR;
01147 AT91_REG US_CSR;
01148 AT91_REG US_RHR;
01149 AT91_REG US_THR;
01150 AT91_REG US_BRGR;
01151 AT91_REG US_RTOR;
01152 AT91_REG US_TTGR;
01153 AT91_REG Reserved0[5];
01154 AT91_REG US_FIDI;
01155 AT91_REG US_NER;
01156 AT91_REG Reserved1[1];
01157 AT91_REG US_IF;
01158 AT91_REG Reserved2[44];
01159 AT91_REG US_RPR;
01160 AT91_REG US_RCR;
01161 AT91_REG US_TPR;
01162 AT91_REG US_TCR;
01163 AT91_REG US_RNPR;
01164 AT91_REG US_RNCR;
01165 AT91_REG US_TNPR;
01166 AT91_REG US_TNCR;
01167 AT91_REG US_PTCR;
01168 AT91_REG US_PTSR;
01169 } AT91S_USART, *AT91PS_USART;
01170 #else
01171 #define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
01172 #define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
01173 #define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
01174 #define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
01175 #define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
01176 #define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
01177 #define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
01178 #define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
01179 #define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
01180 #define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
01181 #define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
01182 #define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
01183 #define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
01184 #define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
01185
01186 #endif
01187
01188 #define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
01189 #define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
01190 #define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
01191 #define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
01192 #define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
01193 #define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
01194 #define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
01195 #define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
01196 #define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
01197 #define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
01198 #define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
01199
01200 #define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
01201 #define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
01202 #define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
01203 #define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
01204 #define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
01205 #define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
01206 #define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
01207 #define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
01208 #define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
01209 #define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
01210 #define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
01211 #define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
01212 #define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
01213 #define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
01214 #define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
01215 #define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
01216 #define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
01217 #define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
01218 #define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
01219 #define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
01220 #define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
01221 #define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
01222 #define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
01223 #define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
01224 #define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
01225 #define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
01226 #define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
01227 #define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
01228 #define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
01229 #define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
01230 #define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
01231 #define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
01232
01233 #define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
01234 #define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
01235 #define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
01236 #define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
01237 #define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
01238 #define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
01239 #define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
01240 #define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
01241
01242
01243
01244 #define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
01245 #define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
01246 #define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
01247 #define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
01248
01249
01250
01251
01252 #ifndef __ASSEMBLY__
01253 typedef struct _AT91S_TWI {
01254 AT91_REG TWI_CR;
01255 AT91_REG TWI_MMR;
01256 AT91_REG Reserved0[1];
01257 AT91_REG TWI_IADR;
01258 AT91_REG TWI_CWGR;
01259 AT91_REG Reserved1[3];
01260 AT91_REG TWI_SR;
01261 AT91_REG TWI_IER;
01262 AT91_REG TWI_IDR;
01263 AT91_REG TWI_IMR;
01264 AT91_REG TWI_RHR;
01265 AT91_REG TWI_THR;
01266 AT91_REG Reserved2[50];
01267 AT91_REG TWI_RPR;
01268 AT91_REG TWI_RCR;
01269 AT91_REG TWI_TPR;
01270 AT91_REG TWI_TCR;
01271 AT91_REG TWI_RNPR;
01272 AT91_REG TWI_RNCR;
01273 AT91_REG TWI_TNPR;
01274 AT91_REG TWI_TNCR;
01275 AT91_REG TWI_PTCR;
01276 AT91_REG TWI_PTSR;
01277 } AT91S_TWI, *AT91PS_TWI;
01278 #else
01279 #define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
01280 #define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
01281 #define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
01282 #define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
01283 #define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
01284 #define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
01285 #define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
01286 #define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
01287 #define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
01288 #define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
01289
01290 #endif
01291
01292 #define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
01293 #define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
01294 #define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
01295 #define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
01296 #define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
01297
01298 #define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
01299 #define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
01300 #define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
01301 #define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
01302 #define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
01303 #define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
01304 #define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
01305
01306 #define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
01307 #define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
01308 #define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
01309
01310 #define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
01311 #define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
01312 #define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
01313 #define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
01314 #define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
01315 #define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
01316 #define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
01317 #define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
01318 #define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
01319 #define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
01320
01321
01322
01323
01324
01325
01326
01327 #ifndef __ASSEMBLY__
01328 typedef struct _AT91S_TC {
01329 AT91_REG TC_CCR;
01330 AT91_REG TC_CMR;
01331 AT91_REG Reserved0[2];
01332 AT91_REG TC_CV;
01333 AT91_REG TC_RA;
01334 AT91_REG TC_RB;
01335 AT91_REG TC_RC;
01336 AT91_REG TC_SR;
01337 AT91_REG TC_IER;
01338 AT91_REG TC_IDR;
01339 AT91_REG TC_IMR;
01340 } AT91S_TC, *AT91PS_TC;
01341 #else
01342 #define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
01343 #define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
01344 #define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
01345 #define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
01346 #define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
01347 #define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
01348 #define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
01349 #define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
01350 #define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
01351 #define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
01352
01353 #endif
01354
01355 #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
01356 #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
01357 #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
01358
01359 #define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
01360 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
01361 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
01362 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
01363 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
01364 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
01365 #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
01366 #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
01367 #define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
01368 #define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
01369 #define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
01370 #define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
01371 #define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
01372 #define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
01373 #define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
01374 #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
01375 #define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
01376 #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
01377 #define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
01378 #define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
01379 #define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
01380 #define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
01381 #define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
01382 #define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
01383 #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
01384 #define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
01385 #define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
01386 #define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
01387 #define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
01388 #define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
01389 #define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
01390 #define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
01391 #define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
01392 #define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
01393 #define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
01394 #define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
01395 #define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
01396 #define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
01397 #define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
01398 #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
01399 #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
01400 #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
01401 #define AT91C_TC_WAVE (0x1 << 15) // (TC)
01402 #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
01403 #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
01404 #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
01405 #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
01406 #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
01407 #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
01408 #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
01409 #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
01410 #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
01411 #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
01412 #define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
01413 #define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
01414 #define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
01415 #define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
01416 #define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
01417 #define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
01418 #define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
01419 #define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
01420 #define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
01421 #define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
01422 #define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
01423 #define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
01424 #define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
01425 #define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
01426 #define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
01427 #define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
01428 #define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
01429 #define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
01430 #define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
01431 #define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
01432 #define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
01433 #define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
01434 #define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
01435 #define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
01436 #define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
01437 #define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
01438 #define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
01439 #define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
01440 #define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
01441 #define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
01442 #define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
01443 #define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
01444 #define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
01445 #define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
01446 #define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
01447 #define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
01448 #define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
01449 #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
01450 #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
01451 #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
01452
01453 #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
01454 #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
01455 #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
01456 #define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
01457 #define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
01458 #define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
01459 #define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
01460 #define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
01461 #define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
01462 #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
01463 #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
01464
01465
01466
01467
01468
01469
01470
01471 #ifndef __ASSEMBLY__
01472 typedef struct _AT91S_TCB {
01473 AT91S_TC TCB_TC0;
01474 AT91_REG Reserved0[4];
01475 AT91S_TC TCB_TC1;
01476 AT91_REG Reserved1[4];
01477 AT91S_TC TCB_TC2;
01478 AT91_REG Reserved2[4];
01479 AT91_REG TCB_BCR;
01480 AT91_REG TCB_BMR;
01481 } AT91S_TCB, *AT91PS_TCB;
01482 #else
01483 #define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
01484 #define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
01485
01486 #endif
01487
01488 #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
01489
01490 #define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
01491 #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
01492 #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
01493 #define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
01494 #define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
01495 #define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
01496 #define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
01497 #define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
01498 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
01499 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
01500 #define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
01501 #define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
01502 #define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
01503 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
01504 #define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
01505
01506
01507
01508
01509 #ifndef __ASSEMBLY__
01510 typedef struct _AT91S_PWMC_CH {
01511 AT91_REG PWMC_CMR;
01512 AT91_REG PWMC_CDTYR;
01513 AT91_REG PWMC_CPRDR;
01514 AT91_REG PWMC_CCNTR;
01515 AT91_REG PWMC_CUPDR;
01516 AT91_REG PWMC_Reserved[3];
01517 } AT91S_PWMC_CH, *AT91PS_PWMC_CH;
01518 #else
01519 #define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
01520 #define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
01521 #define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
01522 #define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
01523 #define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
01524 #define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
01525
01526 #endif
01527
01528 #define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
01529 #define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
01530 #define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
01531 #define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
01532 #define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
01533 #define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
01534 #define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
01535
01536 #define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
01537
01538 #define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
01539
01540 #define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
01541
01542 #define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
01543
01544
01545
01546
01547 #ifndef __ASSEMBLY__
01548 typedef struct _AT91S_PWMC {
01549 AT91_REG PWMC_MR;
01550 AT91_REG PWMC_ENA;
01551 AT91_REG PWMC_DIS;
01552 AT91_REG PWMC_SR;
01553 AT91_REG PWMC_IER;
01554 AT91_REG PWMC_IDR;
01555 AT91_REG PWMC_IMR;
01556 AT91_REG PWMC_ISR;
01557 AT91_REG Reserved0[55];
01558 AT91_REG PWMC_VR;
01559 AT91_REG Reserved1[64];
01560 AT91S_PWMC_CH PWMC_CH[4];
01561 } AT91S_PWMC, *AT91PS_PWMC;
01562 #else
01563 #define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
01564 #define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
01565 #define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
01566 #define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
01567 #define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
01568 #define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
01569 #define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
01570 #define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
01571 #define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
01572
01573 #endif
01574
01575 #define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
01576 #define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
01577 #define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
01578 #define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
01579 #define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
01580 #define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
01581
01582 #define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
01583 #define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
01584 #define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
01585 #define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
01586
01587
01588
01589
01590
01591
01592
01593
01594
01595
01596 #ifndef __ASSEMBLY__
01597 typedef struct _AT91S_UDP {
01598 AT91_REG UDP_NUM;
01599 AT91_REG UDP_GLBSTATE;
01600 AT91_REG UDP_FADDR;
01601 AT91_REG Reserved0[1];
01602 AT91_REG UDP_IER;
01603 AT91_REG UDP_IDR;
01604 AT91_REG UDP_IMR;
01605 AT91_REG UDP_ISR;
01606 AT91_REG UDP_ICR;
01607 AT91_REG Reserved1[1];
01608 AT91_REG UDP_RSTEP;
01609 AT91_REG Reserved2[1];
01610 AT91_REG UDP_CSR[4];
01611 AT91_REG Reserved3[4];
01612 AT91_REG UDP_FDR[4];
01613 AT91_REG Reserved4[5];
01614 AT91_REG UDP_TXVC;
01615 } AT91S_UDP, *AT91PS_UDP;
01616 #else
01617 #define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
01618 #define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
01619 #define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
01620 #define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
01621 #define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
01622 #define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
01623 #define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
01624 #define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
01625 #define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
01626 #define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
01627 #define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
01628 #define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
01629
01630 #endif
01631
01632 #define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
01633 #define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
01634 #define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
01635
01636 #define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
01637 #define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
01638 #define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
01639 #define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
01640 #define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
01641
01642 #define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
01643 #define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
01644
01645 #define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
01646 #define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
01647 #define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
01648 #define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
01649 #define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
01650 #define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
01651 #define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
01652 #define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
01653 #define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
01654
01655
01656
01657 #define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
01658
01659
01660 #define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
01661 #define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
01662 #define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
01663 #define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
01664
01665 #define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
01666 #define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
01667 #define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
01668 #define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
01669 #define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
01670 #define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
01671 #define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
01672 #define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
01673 #define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
01674 #define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
01675 #define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
01676 #define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
01677 #define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
01678 #define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
01679 #define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
01680 #define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
01681 #define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
01682 #define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
01683 #define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
01684 #define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
01685
01686 #define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
01687
01688
01689
01690
01691
01692
01693 #define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
01694 #define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
01695 #define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
01696 #define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
01697 #define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
01698 #define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
01699 #define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
01700 #define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
01701 #define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
01702 #define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
01703 #define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
01704 #define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
01705 #define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
01706 #define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
01707 #define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
01708 #define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
01709 #define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
01710 #define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
01711
01712 #define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
01713 #define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
01714 #define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
01715 #define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
01716 #define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
01717 #define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
01718 #define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
01719 #define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
01720 #define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
01721 #define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
01722
01723 #define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
01724 #define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
01725 #define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
01726 #define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
01727 #define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
01728 #define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
01729 #define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
01730 #define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
01731 #define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
01732 #define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
01733 #define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
01734 #define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
01735
01736 #define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
01737 #define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
01738 #define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
01739 #define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
01740 #define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
01741 #define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
01742 #define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
01743 #define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
01744 #define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
01745 #define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
01746 #define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
01747 #define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
01748 #define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
01749 #define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
01750 #define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
01751 #define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
01752 #define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
01753 #define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
01754 #define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
01755 #define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
01756 #define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
01757 #define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
01758 #define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
01759 #define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
01760 #define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
01761 #define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
01762 #define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
01763 #define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
01764 #define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
01765
01766 #define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
01767 #define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
01768 #define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
01769
01770 #define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
01771 #define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
01772 #define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
01773 #define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
01774 #define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
01775 #define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
01776 #define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
01777 #define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
01778 #define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
01779 #define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
01780 #define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
01781 #define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
01782 #define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
01783 #define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
01784 #define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
01785
01786 #define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
01787 #define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
01788 #define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
01789
01790 #define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
01791 #define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
01792 #define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
01793 #define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
01794
01795 #define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
01796 #define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
01797 #define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
01798 #define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
01799
01800 #define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
01801 #define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
01802 #define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
01803
01804 #define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
01805
01806 #define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
01807 #define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
01808 #define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
01809 #define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
01810 #define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
01811 #define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
01812
01813 #define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
01814 #define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
01815 #define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
01816 #define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
01817 #define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
01818 #define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
01819 #define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
01820 #define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
01821 #define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
01822 #define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
01823
01824 #define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
01825 #define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register
01826 #define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
01827 #define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register
01828 #define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
01829 #define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
01830 #define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
01831 #define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
01832 #define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
01833
01834 #define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
01835 #define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
01836 #define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
01837 #define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
01838 #define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
01839 #define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
01840 #define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
01841 #define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
01842 #define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
01843 #define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
01844
01845 #define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
01846 #define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
01847 #define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
01848 #define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
01849 #define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
01850 #define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
01851 #define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
01852 #define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
01853 #define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
01854 #define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
01855 #define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
01856 #define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
01857 #define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
01858 #define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
01859 #define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
01860 #define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
01861 #define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
01862 #define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
01863
01864 #define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
01865 #define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
01866 #define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
01867 #define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
01868 #define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
01869 #define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
01870 #define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
01871 #define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
01872 #define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
01873 #define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
01874
01875 #define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
01876 #define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
01877 #define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
01878 #define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
01879 #define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
01880 #define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
01881 #define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
01882 #define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
01883 #define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
01884 #define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
01885 #define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
01886 #define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
01887 #define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
01888 #define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
01889
01890 #define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
01891 #define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
01892 #define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
01893 #define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
01894 #define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
01895 #define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
01896 #define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
01897 #define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
01898 #define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
01899 #define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
01900
01901 #define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
01902 #define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
01903 #define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
01904 #define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
01905 #define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
01906 #define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
01907 #define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
01908 #define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
01909 #define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
01910 #define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
01911 #define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
01912 #define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
01913 #define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
01914 #define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
01915
01916 #define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
01917 #define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
01918 #define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
01919 #define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
01920 #define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
01921 #define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
01922 #define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
01923 #define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
01924 #define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
01925 #define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
01926
01927 #define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
01928 #define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
01929 #define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
01930 #define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
01931 #define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
01932 #define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
01933 #define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
01934 #define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
01935 #define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
01936 #define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
01937 #define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
01938 #define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
01939 #define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
01940 #define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
01941
01942 #define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
01943 #define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
01944 #define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
01945 #define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
01946 #define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
01947 #define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
01948 #define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
01949 #define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
01950 #define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
01951 #define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
01952
01953 #define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
01954 #define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
01955 #define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
01956 #define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
01957 #define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
01958 #define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
01959 #define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
01960 #define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
01961 #define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
01962 #define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
01963
01964 #define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
01965 #define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
01966 #define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
01967 #define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
01968 #define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
01969 #define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
01970 #define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
01971 #define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
01972 #define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
01973 #define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
01974
01975 #define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
01976 #define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
01977 #define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
01978 #define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
01979 #define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
01980 #define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
01981 #define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
01982 #define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
01983 #define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
01984 #define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
01985
01986 #define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
01987 #define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
01988
01989 #define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
01990 #define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
01991 #define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
01992 #define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
01993 #define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
01994 #define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
01995
01996 #define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
01997 #define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
01998 #define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
01999 #define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
02000 #define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
02001 #define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
02002
02003 #define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
02004 #define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
02005 #define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
02006 #define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
02007 #define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
02008 #define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
02009
02010 #define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
02011 #define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
02012 #define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
02013 #define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
02014 #define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
02015 #define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
02016
02017 #define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
02018 #define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
02019 #define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
02020 #define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
02021 #define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
02022 #define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
02023 #define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
02024 #define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
02025 #define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
02026
02027 #define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
02028 #define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
02029 #define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
02030 #define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
02031 #define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
02032 #define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
02033 #define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
02034 #define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
02035 #define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
02036 #define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
02037 #define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
02038 #define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
02039
02040
02041
02042
02043 #define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
02044 #define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
02045 #define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
02046 #define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
02047 #define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
02048 #define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
02049 #define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
02050 #define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
02051 #define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
02052 #define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
02053 #define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
02054 #define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
02055 #define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
02056 #define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
02057 #define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
02058 #define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
02059 #define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
02060 #define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
02061 #define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
02062 #define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
02063 #define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
02064 #define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
02065 #define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
02066 #define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
02067 #define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
02068 #define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
02069 #define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
02070 #define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
02071 #define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
02072 #define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
02073 #define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
02074 #define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
02075 #define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
02076 #define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
02077 #define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
02078 #define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
02079 #define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
02080 #define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
02081 #define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
02082 #define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
02083 #define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
02084 #define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
02085 #define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
02086 #define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
02087 #define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
02088 #define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
02089 #define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
02090 #define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
02091 #define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
02092 #define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
02093 #define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
02094 #define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
02095 #define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
02096 #define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
02097 #define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
02098 #define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
02099 #define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
02100 #define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
02101 #define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
02102 #define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
02103 #define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
02104 #define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
02105 #define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
02106 #define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
02107 #define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
02108 #define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
02109 #define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
02110 #define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
02111 #define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
02112 #define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
02113 #define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
02114 #define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
02115 #define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
02116 #define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
02117 #define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
02118 #define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
02119 #define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
02120 #define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
02121 #define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
02122 #define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
02123 #define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
02124 #define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
02125 #define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
02126 #define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
02127 #define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
02128 #define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
02129 #define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
02130 #define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
02131 #define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
02132 #define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
02133 #define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
02134 #define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
02135 #define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
02136 #define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
02137 #define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
02138 #define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
02139
02140
02141
02142
02143 #define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
02144 #define AT91C_ID_SYS ( 1) // System Peripheral
02145 #define AT91C_ID_PIOA ( 2) // Parallel IO Controller
02146 #define AT91C_ID_3_Reserved ( 3) // Reserved
02147 #define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
02148 #define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
02149 #define AT91C_ID_US0 ( 6) // USART 0
02150 #define AT91C_ID_US1 ( 7) // USART 1
02151 #define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
02152 #define AT91C_ID_TWI ( 9) // Two-Wire Interface
02153 #define AT91C_ID_PWMC (10) // PWM Controller
02154 #define AT91C_ID_UDP (11) // USB Device Port
02155 #define AT91C_ID_TC0 (12) // Timer Counter 0
02156 #define AT91C_ID_TC1 (13) // Timer Counter 1
02157 #define AT91C_ID_TC2 (14) // Timer Counter 2
02158 #define AT91C_ID_15_Reserved (15) // Reserved
02159 #define AT91C_ID_16_Reserved (16) // Reserved
02160 #define AT91C_ID_17_Reserved (17) // Reserved
02161 #define AT91C_ID_18_Reserved (18) // Reserved
02162 #define AT91C_ID_19_Reserved (19) // Reserved
02163 #define AT91C_ID_20_Reserved (20) // Reserved
02164 #define AT91C_ID_21_Reserved (21) // Reserved
02165 #define AT91C_ID_22_Reserved (22) // Reserved
02166 #define AT91C_ID_23_Reserved (23) // Reserved
02167 #define AT91C_ID_24_Reserved (24) // Reserved
02168 #define AT91C_ID_25_Reserved (25) // Reserved
02169 #define AT91C_ID_26_Reserved (26) // Reserved
02170 #define AT91C_ID_27_Reserved (27) // Reserved
02171 #define AT91C_ID_28_Reserved (28) // Reserved
02172 #define AT91C_ID_29_Reserved (29) // Reserved
02173 #define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
02174 #define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
02175 #define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS
02176
02177
02178
02179
02180 #define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
02181 #define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
02182 #define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
02183 #define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
02184 #define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
02185 #define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
02186 #define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
02187 #define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
02188 #define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
02189 #define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
02190 #define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
02191 #define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
02192 #define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
02193 #define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
02194 #define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
02195 #define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
02196 #define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
02197 #define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
02198 #define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
02199 #define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
02200 #define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
02201 #define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
02202 #define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
02203 #define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
02204 #define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
02205 #define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
02206 #define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
02207 #define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
02208 #define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
02209 #define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
02210 #define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
02211 #define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
02212 #define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
02213 #define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
02214
02215
02216
02217
02218
02219 #define AT91C_ISRAM (0x00200000) // Internal SRAM base address
02220 #define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes)
02221
02222 #define AT91C_IFLASH (0x00100000) // Internal FLASH base address
02223 #define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes)
02224 #define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
02225 #define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
02226 #define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes
02227 #define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes
02228
02229 #endif
