00001 /** 00002 * @file 00003 * @brief This file contains RF230-formatted register definitions for the atmega128rfa1 00004 */ 00005 /* Copyright (c) 2008, Swedish Institute of Computer Science 00006 00007 All rights reserved. 00008 00009 Redistribution and use in source and binary forms, with or without 00010 modification, are permitted provided that the following conditions are met: 00011 00012 * Redistributions of source code must retain the above copyright 00013 notice, this list of conditions and the following disclaimer. 00014 * Redistributions in binary form must reproduce the above copyright 00015 notice, this list of conditions and the following disclaimer in 00016 the documentation and/or other materials provided with the 00017 distribution. 00018 * Neither the name of the copyright holders nor the names of 00019 contributors may be used to endorse or promote products derived 00020 from this software without specific prior written permission. 00021 00022 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00025 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 00026 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00027 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00028 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00029 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00030 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00031 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00032 POSSIBILITY OF SUCH DAMAGE. 00033 */ 00034 00035 #ifndef PHY128RFA1_REGISTERMAP_EXTERNAL_H 00036 #define PHY128RFA1_REGISTERMAP_EXTERNAL_H 00037 00038 /* RF230 register access is through SPI which transfers 8 bits address/8 bits data. 00039 * ATmega128rfa1 registers are defined in I/O space, e.g. in gcc /include/avr/iom128rfa1.h 00040 * A typical definition is #define TRX_STATUS _SFR_MEM8(0x141) 00041 * Registers can be read with a macro, but the args for subregisters don't expand properly so the actual address 00042 * is used with explicit _SFR_MEM8 in the subregister read/write routines. 00043 */ 00044 #define SR_TRX_STATUS 0x141, 0x1f, 0 00045 #define SR_TRX_CMD 0x142, 0x1f, 0 00046 #define STATE_TRANSITION (31) 00047 #define SR_TX_PWR 0x145, 0x0f, 0 00048 #define RG_VERSION_NUM VERSION_NUM 00049 #define RG_MAN_ID_0 MAN_ID_0 00050 #define RG_IRQ_MASK IRQ_MASK 00051 #define SR_MAX_FRAME_RETRIES 0x16C, 0xf0, 4 00052 #define SR_TX_AUTO_CRC_ON 0x144, 0x20, 5 00053 #define SR_TRAC_STATUS 0x142, 0xe0, 5 00054 #define SR_CHANNEL 0x148, 0x1f, 0 00055 #define RG_PAN_ID_0 PAN_ID_0 00056 #define RG_PAN_ID_1 PAN_ID_1 00057 #define RG_SHORT_ADDR_0 SHORT_ADDR_0 00058 #define RG_SHORT_ADDR_1 SHORT_ADDR_1 00059 #define RG_IEEE_ADDR_0 IEEE_ADDR_0 00060 #define RG_IEEE_ADDR_1 IEEE_ADDR_1 00061 #define RG_IEEE_ADDR_2 IEEE_ADDR_2 00062 #define RG_IEEE_ADDR_3 IEEE_ADDR_3 00063 #define RG_IEEE_ADDR_4 IEEE_ADDR_4 00064 #define RG_IEEE_ADDR_5 IEEE_ADDR_5 00065 #define RG_IEEE_ADDR_6 IEEE_ADDR_6 00066 #define RG_IEEE_ADDR_7 IEEE_ADDR_7 00067 //#define SR_ED_LEVEL 0x147, 0xff, 0 00068 #define RG_PHY_ED_LEVEL PHY_ED_LEVEL 00069 #define SR_RSSI 0x146, 0x1f, 0 00070 #define SR_PLL_CF_START 0x1a, 0x80, 7 00071 #define SR_PLL_DCU_START 0x1b, 0x80, 7 00072 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 00073 #define RG_CSMA_BE CSMA_BE 00074 #define RG_CSMA_SEED_0 CSMA_SEED_0 00075 #define RG_PHY_RSSI PHY_RSSI 00076 #define SR_CCA_MODE 0x08, 0x60, 5 00077 //#define SR_CCA_CS_THRES 0x09, 0xf0, 4 00078 #define SR_CCA_ED_THRES 0x09, 0x0f, 0 00079 #define SR_CCA_REQUEST 0x08, 0x80, 7 00080 #define SR_CCA_DONE 0x01, 0x80, 7 00081 #define SR_CCA_STATUS 0x01, 0x40, 6 00082 00083 00084 /* RF230 register assignments, for reference */ 00085 #if 0 00086 #define HAVE_REGISTER_MAP (1) 00087 /** Offset for register TRX_STATUS */ 00088 #define RG_TRX_STATUS (0x01) 00089 /** Access parameters for sub-register CCA_DONE in register @ref RG_TRX_STATUS */ 00090 #define SR_CCA_DONE 0x01, 0x80, 7 00091 /** Access parameters for sub-register CCA_STATUS in register @ref RG_TRX_STATUS */ 00092 #define SR_CCA_STATUS 0x01, 0x40, 6 00093 #define SR_reserved_01_3 0x01, 0x20, 5 00094 /** Access parameters for sub-register TRX_STATUS in register @ref RG_TRX_STATUS */ 00095 #define SR_TRX_STATUS 0x01, 0x1f, 0 00096 /** Constant P_ON for sub-register @ref SR_TRX_STATUS */ 00097 #define P_ON (0) 00098 /** Constant BUSY_RX for sub-register @ref SR_TRX_STATUS */ 00099 #define BUSY_RX (1) 00100 /** Constant BUSY_TX for sub-register @ref SR_TRX_STATUS */ 00101 #define BUSY_TX (2) 00102 /** Constant RX_ON for sub-register @ref SR_TRX_STATUS */ 00103 #define RX_ON (6) 00104 /** Constant TRX_OFF for sub-register @ref SR_TRX_STATUS */ 00105 #define TRX_OFF (8) 00106 /** Constant PLL_ON for sub-register @ref SR_TRX_STATUS */ 00107 #define PLL_ON (9) 00108 /** Constant SLEEP for sub-register @ref SR_TRX_STATUS */ 00109 #define SLEEP (15) 00110 /** Constant BUSY_RX_AACK for sub-register @ref SR_TRX_STATUS */ 00111 #define BUSY_RX_AACK (17) 00112 /** Constant BUSY_TX_ARET for sub-register @ref SR_TRX_STATUS */ 00113 #define BUSY_TX_ARET (18) 00114 /** Constant RX_AACK_ON for sub-register @ref SR_TRX_STATUS */ 00115 #define RX_AACK_ON (22) 00116 /** Constant TX_ARET_ON for sub-register @ref SR_TRX_STATUS */ 00117 #define TX_ARET_ON (25) 00118 /** Constant RX_ON_NOCLK for sub-register @ref SR_TRX_STATUS */ 00119 #define RX_ON_NOCLK (28) 00120 /** Constant RX_AACK_ON_NOCLK for sub-register @ref SR_TRX_STATUS */ 00121 #define RX_AACK_ON_NOCLK (29) 00122 /** Constant BUSY_RX_AACK_NOCLK for sub-register @ref SR_TRX_STATUS */ 00123 #define BUSY_RX_AACK_NOCLK (30) 00124 /** Constant STATE_TRANSITION for sub-register @ref SR_TRX_STATUS */ 00125 #define STATE_TRANSITION (31) 00126 00127 /** Offset for register TRX_STATE */ 00128 #define RG_TRX_STATE (0x02) 00129 /** Access parameters for sub-register TRAC_STATUS in register @ref RG_TRX_STATE */ 00130 #define SR_TRAC_STATUS 0x02, 0xe0, 5 00131 /** Access parameters for sub-register TRX_CMD in register @ref RG_TRX_STATE */ 00132 #define SR_TRX_CMD 0x02, 0x1f, 0 00133 /** Constant CMD_NOP for sub-register @ref SR_TRX_CMD */ 00134 #define CMD_NOP (0) 00135 /** Constant CMD_TX_START for sub-register @ref SR_TRX_CMD */ 00136 #define CMD_TX_START (2) 00137 /** Constant CMD_FORCE_TRX_OFF for sub-register @ref SR_TRX_CMD */ 00138 #define CMD_FORCE_TRX_OFF (3) 00139 /** Constant CMD_RX_ON for sub-register @ref SR_TRX_CMD */ 00140 #define CMD_RX_ON (6) 00141 /** Constant CMD_TRX_OFF for sub-register @ref SR_TRX_CMD */ 00142 #define CMD_TRX_OFF (8) 00143 /** Constant CMD_PLL_ON for sub-register @ref SR_TRX_CMD */ 00144 #define CMD_PLL_ON (9) 00145 /** Constant CMD_RX_AACK_ON for sub-register @ref SR_TRX_CMD */ 00146 #define CMD_RX_AACK_ON (22) 00147 /** Constant CMD_TX_ARET_ON for sub-register @ref SR_TRX_CMD */ 00148 #define CMD_TX_ARET_ON (25) 00149 /** Offset for register TRX_CTRL_0 */ 00150 #define RG_TRX_CTRL_0 (0x03) 00151 /** Offset for register TRX_CTRL_1 */ 00152 #define RG_TRX_CTRL_1 (0x04) 00153 /** Access parameters for sub-register PAD_IO in register @ref RG_TRX_CTRL_0 */ 00154 #define SR_PAD_IO 0x03, 0xc0, 6 00155 /** Access parameters for sub-register PAD_IO_CLKM in register @ref RG_TRX_CTRL_0 */ 00156 #define SR_PAD_IO_CLKM 0x03, 0x30, 4 00157 /** Constant CLKM_2mA for sub-register @ref SR_PAD_IO_CLKM */ 00158 #define CLKM_2mA (0) 00159 /** Constant CLKM_4mA for sub-register @ref SR_PAD_IO_CLKM */ 00160 #define CLKM_4mA (1) 00161 /** Constant CLKM_6mA for sub-register @ref SR_PAD_IO_CLKM */ 00162 #define CLKM_6mA (2) 00163 /** Constant CLKM_8mA for sub-register @ref SR_PAD_IO_CLKM */ 00164 #define CLKM_8mA (3) 00165 /** Access parameters for sub-register CLKM_SHA_SEL in register @ref RG_TRX_CTRL_0 */ 00166 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 00167 /** Access parameters for sub-register CLKM_CTRL in register @ref RG_TRX_CTRL_0 */ 00168 #define SR_CLKM_CTRL 0x03, 0x07, 0 00169 /** Constant CLKM_no_clock for sub-register @ref SR_CLKM_CTRL */ 00170 #define CLKM_no_clock (0) 00171 /** Constant CLKM_1MHz for sub-register @ref SR_CLKM_CTRL */ 00172 #define CLKM_1MHz (1) 00173 /** Constant CLKM_2MHz for sub-register @ref SR_CLKM_CTRL */ 00174 #define CLKM_2MHz (2) 00175 /** Constant CLKM_4MHz for sub-register @ref SR_CLKM_CTRL */ 00176 #define CLKM_4MHz (3) 00177 /** Constant CLKM_8MHz for sub-register @ref SR_CLKM_CTRL */ 00178 #define CLKM_8MHz (4) 00179 /** Constant CLKM_16MHz for sub-register @ref SR_CLKM_CTRL */ 00180 #define CLKM_16MHz (5) 00181 /** Offset for register PHY_TX_PWR */ 00182 #define RG_PHY_TX_PWR (0x05) 00183 /** Access parameters for sub-register TX_AUTO_CRC_ON in register @ref RG_PHY_TX_PWR */ 00184 #define SR_TX_AUTO_CRC_ON 0x05, 0x80, 7 00185 #define SR_reserved_05_2 0x05, 0x70, 4 00186 /** Access parameters for sub-register TX_PWR in register @ref RG_PHY_TX_PWR */ 00187 #define SR_TX_PWR 0x05, 0x0f, 0 00188 /** Offset for register PHY_RSSI */ 00189 #define RG_PHY_RSSI (0x06) 00190 #define SR_reserved_06_1 0x06, 0xe0, 5 00191 /** Access parameters for sub-register RSSI in register @ref RG_PHY_RSSI */ 00192 #define SR_RSSI 0x06, 0x1f, 0 00193 /** Offset for register PHY_ED_LEVEL */ 00194 #define RG_PHY_ED_LEVEL (0x07) 00195 /** Access parameters for sub-register ED_LEVEL in register @ref RG_PHY_ED_LEVEL */ 00196 #define SR_ED_LEVEL 0x07, 0xff, 0 00197 /** Offset for register PHY_CC_CCA */ 00198 #define RG_PHY_CC_CCA (0x08) 00199 /** Access parameters for sub-register CCA_REQUEST in register @ref RG_PHY_CC_CCA */ 00200 #define SR_CCA_REQUEST 0x08, 0x80, 7 00201 /** Access parameters for sub-register CCA_MODE in register @ref RG_PHY_CC_CCA */ 00202 #define SR_CCA_MODE 0x08, 0x60, 5 00203 /** Access parameters for sub-register CHANNEL in register @ref RG_PHY_CC_CCA */ 00204 #define SR_CHANNEL 0x08, 0x1f, 0 00205 /** Offset for register CCA_THRES */ 00206 #define RG_CCA_THRES (0x09) 00207 /** Access parameters for sub-register CCA_CS_THRES in register @ref RG_CCA_THRES */ 00208 #define SR_CCA_CS_THRES 0x09, 0xf0, 4 00209 /** Access parameters for sub-register CCA_ED_THRES in register @ref RG_CCA_THRES */ 00210 #define SR_CCA_ED_THRES 0x09, 0x0f, 0 00211 /** Offset for register IRQ_MASK */ 00212 #define RG_IRQ_MASK (0x0e) 00213 /** Access parameters for sub-register IRQ_MASK in register @ref RG_IRQ_MASK */ 00214 #define SR_IRQ_MASK 0x0e, 0xff, 0 00215 /** Offset for register IRQ_STATUS */ 00216 #define RG_IRQ_STATUS (0x0f) 00217 /** Access parameters for sub-register IRQ_7_BAT_LOW in register @ref RG_IRQ_STATUS */ 00218 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 00219 /** Access parameters for sub-register IRQ_6_TRX_UR in register @ref RG_IRQ_STATUS */ 00220 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 00221 /** Access parameters for sub-register IRQ_5 in register @ref RG_IRQ_STATUS */ 00222 #define SR_IRQ_5 0x0f, 0x20, 5 00223 /** Access parameters for sub-register IRQ_4 in register @ref RG_IRQ_STATUS */ 00224 #define SR_IRQ_4 0x0f, 0x10, 4 00225 /** Access parameters for sub-register IRQ_3_TRX_END in register @ref RG_IRQ_STATUS */ 00226 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 00227 /** Access parameters for sub-register IRQ_2_RX_START in register @ref RG_IRQ_STATUS */ 00228 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 00229 /** Access parameters for sub-register IRQ_1_PLL_UNLOCK in register @ref RG_IRQ_STATUS */ 00230 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 00231 /** Access parameters for sub-register IRQ_0_PLL_LOCK in register @ref RG_IRQ_STATUS */ 00232 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 00233 /** Offset for register VREG_CTRL */ 00234 #define RG_VREG_CTRL (0x10) 00235 /** Access parameters for sub-register AVREG_EXT in register @ref RG_VREG_CTRL */ 00236 #define SR_AVREG_EXT 0x10, 0x80, 7 00237 /** Access parameters for sub-register AVDD_OK in register @ref RG_VREG_CTRL */ 00238 #define SR_AVDD_OK 0x10, 0x40, 6 00239 /** Access parameters for sub-register AVREG_TRIM in register @ref RG_VREG_CTRL */ 00240 #define SR_AVREG_TRIM 0x10, 0x30, 4 00241 /** Constant AVREG_1_80V for sub-register @ref SR_AVREG_TRIM */ 00242 #define AVREG_1_80V (0) 00243 /** Constant AVREG_1_75V for sub-register @ref SR_AVREG_TRIM */ 00244 #define AVREG_1_75V (1) 00245 /** Constant AVREG_1_84V for sub-register @ref SR_AVREG_TRIM */ 00246 #define AVREG_1_84V (2) 00247 /** Constant AVREG_1_88V for sub-register @ref SR_AVREG_TRIM */ 00248 #define AVREG_1_88V (3) 00249 /** Access parameters for sub-register DVREG_EXT in register @ref RG_VREG_CTRL */ 00250 #define SR_DVREG_EXT 0x10, 0x08, 3 00251 /** Access parameters for sub-register DVDD_OK in register @ref RG_VREG_CTRL */ 00252 #define SR_DVDD_OK 0x10, 0x04, 2 00253 /** Access parameters for sub-register DVREG_TRIM in register @ref RG_VREG_CTRL */ 00254 #define SR_DVREG_TRIM 0x10, 0x03, 0 00255 /** Constant DVREG_1_80V for sub-register @ref SR_DVREG_TRIM */ 00256 #define DVREG_1_80V (0) 00257 /** Constant DVREG_1_75V for sub-register @ref SR_DVREG_TRIM */ 00258 #define DVREG_1_75V (1) 00259 /** Constant DVREG_1_84V for sub-register @ref SR_DVREG_TRIM */ 00260 #define DVREG_1_84V (2) 00261 /** Constant DVREG_1_88V for sub-register @ref SR_DVREG_TRIM */ 00262 #define DVREG_1_88V (3) 00263 /** Offset for register BATMON */ 00264 #define RG_BATMON (0x11) 00265 #define SR_reserved_11_1 0x11, 0xc0, 6 00266 /** Access parameters for sub-register BATMON_OK in register @ref RG_BATMON */ 00267 #define SR_BATMON_OK 0x11, 0x20, 5 00268 /** Access parameters for sub-register BATMON_HR in register @ref RG_BATMON */ 00269 #define SR_BATMON_HR 0x11, 0x10, 4 00270 /** Access parameters for sub-register BATMON_VTH in register @ref RG_BATMON */ 00271 #define SR_BATMON_VTH 0x11, 0x0f, 0 00272 /** Offset for register XOSC_CTRL */ 00273 #define RG_XOSC_CTRL (0x12) 00274 /** Offset for register RX_SYN */ 00275 #define RG_RX_SYN 0x15 00276 /** Offset for register XAH_CTRL_1 */ 00277 #define RG_XAH_CTRL_1 0x17 00278 /** Access parameters for sub-register XTAL_MODE in register @ref RG_XOSC_CTRL */ 00279 #define SR_XTAL_MODE 0x12, 0xf0, 4 00280 /** Access parameters for sub-register XTAL_TRIM in register @ref RG_XOSC_CTRL */ 00281 #define SR_XTAL_TRIM 0x12, 0x0f, 0 00282 /** Offset for register FTN_CTRL */ 00283 #define RG_FTN_CTRL (0x18) 00284 /** Access parameters for sub-register FTN_START in register @ref RG_FTN_CTRL */ 00285 #define SR_FTN_START 0x18, 0x80, 7 00286 #define SR_reserved_18_2 0x18, 0x40, 6 00287 /** Access parameters for sub-register FTNV in register @ref RG_FTN_CTRL */ 00288 #define SR_FTNV 0x18, 0x3f, 0 00289 /** Offset for register PLL_CF */ 00290 #define RG_PLL_CF (0x1a) 00291 /** Access parameters for sub-register PLL_CF_START in register @ref RG_PLL_CF */ 00292 #define SR_PLL_CF_START 0x1a, 0x80, 7 00293 #define SR_reserved_1a_2 0x1a, 0x70, 4 00294 /** Access parameters for sub-register PLL_CF in register @ref RG_PLL_CF */ 00295 #define SR_PLL_CF 0x1a, 0x0f, 0 00296 /** Offset for register PLL_DCU */ 00297 #define RG_PLL_DCU (0x1b) 00298 /** Access parameters for sub-register PLL_DCU_START in register @ref RG_PLL_DCU */ 00299 #define SR_PLL_DCU_START 0x1b, 0x80, 7 00300 #define SR_reserved_1b_2 0x1b, 0x40, 6 00301 /** Access parameters for sub-register PLL_DCUW in register @ref RG_PLL_DCU */ 00302 #define SR_PLL_DCUW 0x1b, 0x3f, 0 00303 /** Offset for register PART_NUM */ 00304 #define RG_PART_NUM (0x1c) 00305 /** Access parameters for sub-register PART_NUM in register @ref RG_PART_NUM */ 00306 #define SR_PART_NUM 0x1c, 0xff, 0 00307 /** Constant RF230 for sub-register @ref SR_PART_NUM */ 00308 #define RF230 (2) 00309 /** Offset for register VERSION_NUM */ 00310 #define RG_VERSION_NUM (0x1d) 00311 /** Access parameters for sub-register VERSION_NUM in register @ref RG_VERSION_NUM */ 00312 #define SR_VERSION_NUM 0x1d, 0xff, 0 00313 /** Offset for register MAN_ID_0 */ 00314 #define RG_MAN_ID_0 (0x1e) 00315 /** Access parameters for sub-register MAN_ID_0 in register @ref RG_MAN_ID_0 */ 00316 #define SR_MAN_ID_0 0x1e, 0xff, 0 00317 /** Offset for register MAN_ID_1 */ 00318 #define RG_MAN_ID_1 (0x1f) 00319 /** Access parameters for sub-register MAN_ID_1 in register @ref RG_MAN_ID_1 */ 00320 #define SR_MAN_ID_1 0x1f, 0xff, 0 00321 /** Offset for register SHORT_ADDR_0 */ 00322 #define RG_SHORT_ADDR_0 (0x20) 00323 /** Access parameters for sub-register SHORT_ADDR_0 in register @ref RG_SHORT_ADDR_0 */ 00324 #define SR_SHORT_ADDR_0 0x20, 0xff, 0 00325 /** Offset for register SHORT_ADDR_1 */ 00326 #define RG_SHORT_ADDR_1 (0x21) 00327 /** Access parameters for sub-register SHORT_ADDR_1 in register @ref RG_SHORT_ADDR_1 */ 00328 #define SR_SHORT_ADDR_1 0x21, 0xff, 0 00329 /** Offset for register PAN_ID_0 */ 00330 #define RG_PAN_ID_0 (0x22) 00331 /** Access parameters for sub-register PAN_ID_0 in register @ref RG_PAN_ID_0 */ 00332 #define SR_PAN_ID_0 0x22, 0xff, 0 00333 /** Offset for register PAN_ID_1 */ 00334 #define RG_PAN_ID_1 (0x23) 00335 /** Access parameters for sub-register PAN_ID_1 in register @ref RG_PAN_ID_1 */ 00336 #define SR_PAN_ID_1 0x23, 0xff, 0 00337 /** Offset for register IEEE_ADDR_0 */ 00338 #define RG_IEEE_ADDR_0 (0x24) 00339 /** Access parameters for sub-register IEEE_ADDR_0 in register @ref RG_IEEE_ADDR_0 */ 00340 #define SR_IEEE_ADDR_0 0x24, 0xff, 0 00341 /** Offset for register IEEE_ADDR_1 */ 00342 #define RG_IEEE_ADDR_1 (0x25) 00343 /** Access parameters for sub-register IEEE_ADDR_1 in register @ref RG_IEEE_ADDR_1 */ 00344 #define SR_IEEE_ADDR_1 0x25, 0xff, 0 00345 /** Offset for register IEEE_ADDR_2 */ 00346 #define RG_IEEE_ADDR_2 (0x26) 00347 /** Access parameters for sub-register IEEE_ADDR_2 in register @ref RG_IEEE_ADDR_2 */ 00348 #define SR_IEEE_ADDR_2 0x26, 0xff, 0 00349 /** Offset for register IEEE_ADDR_3 */ 00350 #define RG_IEEE_ADDR_3 (0x27) 00351 /** Access parameters for sub-register IEEE_ADDR_3 in register @ref RG_IEEE_ADDR_3 */ 00352 #define SR_IEEE_ADDR_3 0x27, 0xff, 0 00353 /** Offset for register IEEE_ADDR_4 */ 00354 #define RG_IEEE_ADDR_4 (0x28) 00355 /** Access parameters for sub-register IEEE_ADDR_4 in register @ref RG_IEEE_ADDR_4 */ 00356 #define SR_IEEE_ADDR_4 0x28, 0xff, 0 00357 /** Offset for register IEEE_ADDR_5 */ 00358 #define RG_IEEE_ADDR_5 (0x29) 00359 /** Access parameters for sub-register IEEE_ADDR_5 in register @ref RG_IEEE_ADDR_5 */ 00360 #define SR_IEEE_ADDR_5 0x29, 0xff, 0 00361 /** Offset for register IEEE_ADDR_6 */ 00362 #define RG_IEEE_ADDR_6 (0x2a) 00363 /** Access parameters for sub-register IEEE_ADDR_6 in register @ref RG_IEEE_ADDR_6 */ 00364 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 00365 /** Offset for register IEEE_ADDR_7 */ 00366 #define RG_IEEE_ADDR_7 (0x2b) 00367 /** Access parameters for sub-register IEEE_ADDR_7 in register @ref RG_IEEE_ADDR_7 */ 00368 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 00369 /** Offset for register XAH_CTRL */ 00370 #define RG_XAH_CTRL_0 (0x2c) 00371 /** Access parameters for sub-register MAX_FRAME_RETRIES in register @ref RG_XAH_CTRL_0 */ 00372 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 00373 /** Access parameters for sub-register MAX_CSMA_RETRIES in register @ref RG_XAH_CTRL_0 */ 00374 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 00375 #define SR_reserved_2c_3 0x2c, 0x01, 0 00376 /** Offset for register CSMA_SEED_0 */ 00377 #define RG_CSMA_SEED_0 (0x2d) 00378 /** Access parameters for sub-register CSMA_SEED_0 in register @ref RG_CSMA_SEED_0 */ 00379 #define SR_CSMA_SEED_0 0x2d, 0xff, 0 00380 /** Offset for register CSMA_SEED_1 */ 00381 #define RG_CSMA_SEED_1 (0x2e) 00382 /** Offset for register CSMA_BE */ 00383 #define RG_CSMA_BE 0x2f 00384 /** Access parameters for sub-register MIN_BE in register @ref RG_CSMA_SEED_1 */ 00385 #define SR_MIN_BE 0x2e, 0xc0, 6 00386 #define SR_reserved_2e_2 0x2e, 0x30, 4 00387 /** Access parameters for sub-register I_AM_COORD in register @ref RG_CSMA_SEED_1 */ 00388 #define SR_I_AM_COORD 0x2e, 0x08, 3 00389 /** Access parameters for sub-register CSMA_SEED_1 in register @ref RG_CSMA_SEED_1 */ 00390 #define SR_CSMA_SEED_1 0x2e, 0x07, 0 00391 #endif 00392 #endif /* PHY128RFA1_REGISTERMAP_EXTERNAL_H */
1.6.1