cc2430_sfr.h

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00001 /**
00002  *
00003  * \file cc2430_sfr.h
00004  * \brief CC2430 registers header file for CC2430.
00005  *
00006  *  Definitions for CC2430 SFR registers.
00007  *   
00008  *      
00009  */
00010 
00011 #ifndef REG_CC2430_H
00012 #define REG_CC2430_H
00013 
00014 /*  BYTE Register  */
00015 
00016 __sfr __at (0x80) P0   ;
00017 /* P0 */
00018 __sbit __at (0x87) P0_7 ;
00019 __sbit __at (0x86) P0_6 ;
00020 __sbit __at (0x85) P0_5 ;
00021 __sbit __at (0x84) P0_4 ;
00022 __sbit __at (0x83) P0_3 ;
00023 __sbit __at (0x82) P0_2 ;
00024 __sbit __at (0x81) P0_1 ;
00025 __sbit __at (0x80) P0_0 ;
00026 
00027 __sfr __at (0x81) SP   ;
00028 __sfr __at (0x82) DPL0  ;
00029 __sfr __at (0x83) DPH0  ;
00030 /*DPL and DPH correspond DPL0 and DPH0 (82-83)*/
00031 __sfr __at (0x84)   DPL1;
00032 __sfr __at (0x85)   DPH1;
00033 __sfr __at (0x86)   U0CSR;
00034 #define U_MODE  0x80
00035 #define U_RE    0x40
00036 #define U_SLAVE 0x20
00037 #define U_FE    0x10
00038 #define U_ERR   0x08
00039 #define U_RXB   0x04
00040 #define U_TXB   0x02
00041 #define U_ACTIVE 0x01
00042 
00043 __sfr __at (0x87) PCON ;
00044 /*  PCON (0x87) */
00045 #define IDLE 0x01
00046 
00047 __sfr __at (0x88) TCON ;
00048 /*  TCON (0x88) */
00049 __sbit __at (0x8F) TCON_URX1IF;
00050 /*__sbit __at (0x8E) RES;*/
00051 __sbit __at (0x8D) TCON_ADCIF;
00052 /*__sbit __at (0x8C) RES;*/
00053 __sbit __at (0x8B) TCON_URX0IF;
00054 __sbit __at (0x8A) TCON_IT1;
00055 __sbit __at (0x89) TCON_RFERRIF;
00056 __sbit __at (0x88) TCON_IT0;
00057 
00058 
00059 __sfr __at (0x89)   P0IFG;
00060 __sfr __at (0x8A)   P1IFG;
00061 __sfr __at (0x8B)   P2IFG;
00062 __sfr __at (0x8C)   PICTL;
00063 /*PICTL bits*/
00064 #define PADSC   0x40
00065 #define P2IEN   0x20
00066 #define P0IENH  0x10
00067 #define P0IENL  0x08
00068 #define P2ICON  0x04
00069 #define P1ICON  0x02
00070 #define P0ICON  0x01
00071 
00072 __sfr __at (0x8D)   P1IEN;
00073 __sfr __at (0x8F)   P0INP;
00074 
00075 __sfr __at (0x90) P1   ;
00076 /* P1 */
00077 __sbit __at (0x90) P1_0 ;
00078 __sbit __at (0x91) P1_1 ;
00079 __sbit __at (0x92) P1_2 ;
00080 __sbit __at (0x93) P1_3 ;
00081 __sbit __at (0x94) P1_4 ;
00082 __sbit __at (0x95) P1_5 ;
00083 __sbit __at (0x96) P1_6 ;
00084 __sbit __at (0x97) P1_7 ;
00085 
00086 __sfr __at (0x91)   RFIM;
00087 __sfr __at (0x92)   DPS;
00088 __sfr __at (0x93)   _XPAGE; /*MPAGE as paging register for sdcc*/
00089 __sfr __at (0x94)   T2CMP;
00090 __sfr __at (0x95)   ST0;
00091 __sfr __at (0x96)   ST1;
00092 __sfr __at (0x97)   ST2;
00093 __sfr __at (0x98)   S0CON ;
00094 
00095 __sbit __at (0x99) S0CON_ENCIF_1;
00096 __sbit __at (0x98) S0CON_ENCIF_0;
00097 
00098 __sfr __at (0x99)   HSRC;
00099 __sfr __at (0x9A)   IEN2;
00100 /*IEN2 bits*/
00101 #define WDTIE   0x20
00102 #define P1IE    0x10
00103 #define UTX1IE  0x08
00104 #define UTX0IE  0x04
00105 #define P2IE    0x02
00106 #define RFIE    0x01
00107 __sfr __at (0x9B)   S1CON;
00108 /*S1CON bits*/
00109 #define RFIF_1  0x02
00110 #define RFIF_0  0x01
00111 __sfr __at (0x9C)   T2PEROF0;
00112 __sfr __at (0x9D)   T2PEROF1;
00113 __sfr __at (0x9E)   T2PEROF2;
00114 /*T2PEROF2 bits*/
00115 #define CMPIM   0x80
00116 #define PERIM   0x40
00117 #define OFCMPIM 0x20
00118 
00119 #define PEROF23 0x08
00120 #define PEROF22 0x04
00121 #define PEROF21 0x02
00122 #define PEROF20 0x01
00123 
00124 __sfr __at (0x9F) FMAP;
00125 __sfr __at (0x9F) PSBANK;
00126 
00127 __sfr __at (0xA0) P2   ;
00128 /* P2 */
00129 __sbit __at (0xA0) P2_0 ;
00130 __sbit __at (0xA1) P2_1 ;
00131 __sbit __at (0xA2) P2_2 ;
00132 __sbit __at (0xA3) P2_3 ;
00133 __sbit __at (0xA4) P2_4 ;
00134 /*__sbit __at (0xA5) P2_5 ;
00135 __sbit __at (0xA6) P2_6 ;
00136 __sbit __at (0xA7) P2_7 ;*/
00137 
00138 __sfr __at (0xA1)   T2OF0;
00139 __sfr __at (0xA2)   T2OF1;
00140 __sfr __at (0xA3)   T2OF2;
00141 __sfr __at (0xA4)   T2CAPLPL;
00142 __sfr __at (0xA5)   T2CAPHPH;
00143 __sfr __at (0xA6)   T2TLD;
00144 __sfr __at (0xA7)   T2THD;
00145 
00146 __sfr __at (0xA8) IE   ;
00147 __sfr __at (0xA8)   IEN0;
00148 /*IEN0 bits*/
00149 #define IEN0_EA_MASK    0x80
00150 #define STIE    0x20
00151 #define ENCIE   0x10
00152 #define URX1IE  0x08
00153 #define URX0IE  0x04
00154 #define ADCIE   0x02
00155 #define RFERRIE 0x01
00156 /*  IEN0 (0xA8) */
00157 __sbit __at (0xAF) EA;
00158 __sbit __at (0xAF) IEN0_EA;
00159 /*__sbit __at (0xAE) RES;*/
00160 __sbit __at (0xAD) IEN0_STIE;
00161 __sbit __at (0xAC) IEN0_ENCIE;
00162 __sbit __at (0xAB) IEN0_URX1IE;
00163 __sbit __at (0xAA) IEN0_URX0IE;
00164 __sbit __at (0xA9) IEN0_ADCIE;
00165 __sbit __at (0xA8) IEN0_RFERRIE;
00166 
00167 __sfr __at (0xA9)   IP0;
00168 /*IP0 bits*/
00169 #define IP0_5   0x20
00170 #define IP0_4   0x10
00171 #define IP0_3   0x08
00172 #define IP0_2   0x04
00173 #define IP0_1   0x02
00174 #define IP0_0   0x01
00175 __sfr __at (0xAB)   FWT;
00176 __sfr __at (0xAC)   FADDRL;
00177 __sfr __at (0xAD)   FADDRH;
00178 
00179 __sfr __at (0xAE)   FCTL;
00180 #define F_BUSY  0x80
00181 #define F_SWBSY 0x40
00182 #define F_CONTRD 0x10
00183 #define F_WRITE 0x02
00184 #define F_ERASE 0x01
00185 __sfr __at (0xAF)   FWDATA;
00186 
00187 /*No port 3 (0xB0)*/
00188 __sfr __at (0xB1)   ENCDI;
00189 __sfr __at (0xB2)   ENCDO;
00190 __sfr __at (0xB3)   ENCCS;
00191 #define CCS_MODE2       0x40
00192 #define CCS_MODE1       0x20
00193 #define CCS_MODE0       0x10
00194 #define CCS_RDY         0x08
00195 #define CCS_CMD1        0x04
00196 #define CCS_CMD0        0x02
00197 #define CCS_ST          0x01
00198 __sfr __at (0xB4)   ADCCON1;
00199 /*ADCCON1 bits*/
00200 #define ADEOC   0x80
00201 #define ADST    0x40
00202 #define ADSTS1  0x20
00203 #define ADSTS0  0x10
00204 #define ADRCTRL1        0x08
00205 #define ADRCTRL0        0x04
00206 __sfr __at (0xB5)   ADCCON2;
00207 /*ADCCON2 bits*/
00208 #define ADSREF1 0x80
00209 #define ADSREF0 0x40
00210 #define ADSDIV1 0x20
00211 #define ADSDIV0 0x10
00212 #define ADSCH3  0x08
00213 #define ADSCH2  0x04
00214 #define ADSCH1  0x02
00215 #define ADSCH0  0x01
00216 __sfr __at (0xB6)   ADCCON3;
00217 /*ADCCON3 bits*/
00218 #define ADEREF1 0x80
00219 #define ADEREF0 0x40
00220 #define ADEDIV1 0x20
00221 #define ADEDIV0 0x10
00222 #define ADECH3  0x08
00223 #define ADECH2  0x04
00224 #define ADECH1  0x02
00225 #define ADECH0  0x01
00226 
00227 __sfr __at (0xB7)   RCCTL;
00228 #undef IP  /*this is 0xb8 in base core*/
00229 
00230 __sfr __at (0xB8)   IEN1;
00231 /*IEN1 bits*/
00232 #define P0IE    0x20
00233 #define T4IE    0x10
00234 #define T3IE    0x08
00235 #define T2IE    0x04
00236 #define T1IE    0x02
00237 #define DMAIE   0x01
00238 /*  IEN1 (0xB8) */
00239 /*__sbit __at (0xBF) IEN1_RES;*/
00240 /*__sbit __at (0xBE) RES;*/
00241 __sbit __at (0xBD) IEN1_P0IE;
00242 __sbit __at (0xBC) IEN1_T4IE;
00243 __sbit __at (0xBB) IEN1_T3IE;
00244 __sbit __at (0xBA) IEN1_T2IE;
00245 __sbit __at (0xB9) IEN1_T1IE;
00246 __sbit __at (0xB8) IEN1_DMAIE;
00247 
00248 __sfr __at (0xB9)   IP1;
00249 /*IP1 bits*/
00250 #define IP1_5   0x20
00251 #define IP1_4   0x10
00252 #define IP1_3   0x08
00253 #define IP1_2   0x04
00254 #define IP1_1   0x02
00255 #define IP1_0   0x01
00256 
00257 __sfr __at (0xBA)   ADCL;
00258 __sfr __at (0xBB)   ADCH;
00259 __sfr __at (0xBC)   RNDL;
00260 __sfr __at (0xBD)   RNDH;
00261 
00262 __sfr __at (0xBE)   SLEEP;
00263 #define XOSC_STB        0x40
00264 #define HFRC_STB        0x20
00265 #define RST1            0x10
00266 #define RST0            0x08
00267 #define OSC_PD          0x04
00268 #define SLEEP_MODE1     0x02
00269 #define SLEEP_MODE0     0x01
00270 
00271 __sfr __at (0xC0)   IRCON;
00272 /*IRCON bits*/
00273 #define STIF    0x80
00274 #define P0IF    0x20
00275 #define T4IF    0x10
00276 #define T3IF    0x08
00277 #define T2IF    0x04
00278 #define T1IF    0x02
00279 #define DMAIF   0x01
00280 /* IRCON */
00281 __sbit __at (0xC7) IRCON_STIF ;
00282 /*__sbit __at (0x86) IRCON_6 ;*/
00283 __sbit __at (0xC5) IRCON_P0IF;
00284 __sbit __at (0xC4) IRCON_T4IF;
00285 __sbit __at (0xC3) IRCON_T3IF;
00286 __sbit __at (0xC2) IRCON_T2IF;
00287 __sbit __at (0xC1) IRCON_T1IF;
00288 __sbit __at (0xC0) IRCON_DMAIF;
00289 
00290 __sfr __at (0xC1)   U0BUF;
00291 
00292 __sfr __at (0xC2)   U0BAUD;
00293 __sfr __at (0xC3)   T2CNF;
00294 /*T2SEL bits*/
00295 #define CMPIF   0x80
00296 #define PERIF   0x40
00297 #define OFCMPIF 0x20
00298 
00299 #define CMSEL   0x08
00300 
00301 #define SYNC    0x02
00302 #define RUN     0x01
00303 
00304 __sfr __at (0xC4)   U0UCR;
00305 #define U_FLUSH         0x80
00306 #define U_FLOW          0x40
00307 #define U_D9            0x20
00308 #define U_BIT9          0x10
00309 #define U_PARITY        0x08
00310 #define U_SPB           0x04
00311 #define U_STOP          0x02
00312 #define U_START         0x01
00313 
00314 __sfr __at (0xC5)   U0GCR;
00315 #define U_CPOL          0x80
00316 #define U_CPHA          0x40
00317 #define U_ORDER         0x20
00318 #define U_BAUD_E4       0x10
00319 #define U_BAUD_E3       0x08
00320 #define U_BAUD_E2       0x04
00321 #define U_BAUD_E1       0x02
00322 #define U_BAUD_E0       0x01
00323 
00324 __sfr __at (0xC6)   CLKCON;
00325 #define OSC32K          0x80
00326 #define OSC             0x40
00327 #define TICKSPD2        0x20
00328 #define TICKSPD1        0x10
00329 #define TICKSPD0        0x08
00330 #define CLKSPD          0x01
00331 
00332 __sfr __at (0xC7)   MEMCTR;
00333 #define MUNIF    0x40
00334 __sfr __at (0xC8)   T2CON;
00335 
00336 __sfr __at (0xC9)   WDCTL;
00337 #define WDT_CLR3 0x80
00338 #define WDT_CLR2 0x40
00339 #define WDT_CLR1 0x20
00340 #define WDT_CLR0 0x10
00341 #define WDT_EN   0x08
00342 #define WDT_MODE 0x04
00343 #define WDT_INT1 0x02
00344 #define WDT_INT0 0x01
00345 
00346 __sfr __at (0xCA)   T3CNT;
00347 
00348 __sfr __at (0xCB)   T3CTL;
00349 /*T3CTL bits*/
00350 #define T3DIV2  0x80
00351 #define T3DIV1  0x40
00352 #define T3DIV0  0x20
00353 #define T3START 0x10
00354 #define T3OVFIM 0x08
00355 #define T3CLR   0x04
00356 #define T3MODE1 0x02
00357 #define T3MODE0 0x01
00358 
00359 __sfr __at (0xCC)   T3CCTL0;
00360 /*T3CCTL0 bits*/
00361 #define T3IM    0x40
00362 #define T3CMP2  0x20
00363 #define T3CMP1  0x10
00364 #define T3CMP0  0x08
00365 #define T3MODE  0x04
00366 #define T3CAP1  0x02
00367 #define T3CAP0  0x01
00368 
00369 __sfr __at (0xCD)   T3CC0;
00370 __sfr __at (0xCE)   T3CCTL1;
00371 /*T3CCTL0 bits apply*/
00372 __sfr __at (0xCF)   T3CC1;
00373 
00374 __sfr __at (0xD0) PSW  ;
00375 /*  PSW   */
00376 __sbit __at (0xD0) P    ;
00377 __sbit __at (0xD1) F1   ;
00378 __sbit __at (0xD2) OV   ;
00379 __sbit __at (0xD3) RS0  ;
00380 __sbit __at (0xD4) RS1  ;
00381 __sbit __at (0xD5) F0   ;
00382 __sbit __at (0xD6) AC   ;
00383 __sbit __at (0xD7) CY   ;
00384 
00385 __sfr __at (0xD1)   DMAIRQ;
00386 /*DMAIRQ bits*/
00387 #define DMAIF4  0x10
00388 #define DMAIF3  0x08
00389 #define DMAIF2  0x04
00390 #define DMAIF1  0x02
00391 #define DMAIF0  0x01
00392 
00393 __sfr __at (0xD2)   DMA1CFGL;
00394 __sfr __at (0xD3)   DMA1CFGH;
00395 __sfr __at (0xD4)   DMA0CFGL;
00396 __sfr __at (0xD5)   DMA0CFGH;
00397 
00398 __sfr __at (0xD6)   DMAARM;
00399 /*DMAARM bits*/
00400 #define ABORT   0x80
00401 #define DMAARM4 0x10
00402 #define DMAARM3 0x08
00403 #define DMAARM2 0x04
00404 #define DMAARM1 0x02
00405 #define DMAARM0 0x01
00406 
00407 __sfr __at (0xD7)   DMAREQ;
00408 /*DMAREQ bits*/
00409 #define DMAREQ4 0x10
00410 #define DMAREQ3 0x08
00411 #define DMAREQ2 0x04
00412 #define DMAREQ1 0x02
00413 #define DMAREQ0 0x01
00414 
00415 __sfr __at (0xD8)   TIMIF;
00416 /*TIMIF bits*/
00417 #define OVFIM   0x40
00418 #define T4CH1IF 0x20
00419 #define T4CH0IF 0x10
00420 #define T4OVFIF 0x08
00421 #define T3CH1IF 0x04
00422 #define T3CH0IF 0x02
00423 #define T3OVFIF 0x01
00424 
00425 __sfr __at (0xD9)   RFD;
00426 __sfr __at (0xDA)   T1CC0L;
00427 __sfr __at (0xDB)   T1CC0H;
00428 __sfr __at (0xDC)   T1CC1L;
00429 __sfr __at (0xDD)   T1CC1H;
00430 __sfr __at (0xDE)   T1CC2L;
00431 __sfr __at (0xDF)   T1CC2H;
00432 
00433 __sfr __at (0xE0)   ACC;
00434 __sfr __at (0xE1)   RFST;
00435 __sfr __at (0xE2)   T1CNTL;
00436 __sfr __at (0xE3)   T1CNTH;
00437 
00438 __sfr __at (0xE4)   T1CTL;
00439 /*T1CTL bits*/
00440 #define CH2IF   0x80
00441 #define CH1IF   0x40
00442 #define CH0IF   0x20
00443 #define OVFIF   0x10
00444 #define T1DIV1  0x08
00445 #define T1DIV0  0x04
00446 #define T1MODE1 0x02
00447 #define T1MODE0 0x01
00448 
00449 __sfr __at (0xE5)   T1CCTL0;
00450 /*T1CCTL0 bits*/
00451 #define T1CPSEL 0x80
00452 #define T1IM    0x40
00453 #define T1CMP2  0x20
00454 #define T1CMP1  0x10
00455 #define T1CMP0  0x08
00456 #define T1MODE  0x04
00457 #define T1CAP1  0x02
00458 #define T1CAP0  0x01
00459 
00460 __sfr __at (0xE6)   T1CCTL1;
00461 /*Bits defined in T1CCTL0 */
00462 __sfr __at (0xE7)   T1CCTL2;
00463 /*Bits defined in T1CCTL0 */
00464 __sfr __at (0xE8)   IRCON2;
00465 /*IRCON2 bits*/
00466 #define WDTIF   0x10
00467 #define P1IF    0x08
00468 #define UTX1IF  0x04
00469 #define UTX0IF  0x02
00470 #define P2IF    0x01
00471 /* IRCON 2 */ 
00472 /*__sbit __at (0xEF) IRCON2_P1_7 ;
00473 __sbit __at (0xEE) IRCON2_P1_6 ;
00474 __sbit __at (0xED) IRCON2_P1_5 ;*/
00475 __sbit __at (0xEC) IRCON2_WDTIF ;
00476 __sbit __at (0xEB) IRCON2_P1IF ;
00477 __sbit __at (0xEA) IRCON2_UTX1IF ;
00478 __sbit __at (0xE9) IRCON2_UTX0IF ;
00479 __sbit __at (0xE8) IRCON2_P2IF;
00480 
00481 
00482 __sfr __at (0xE9)   RFIF;
00483 /*RFIF bits*/
00484 #define IRQ_RREG_ON     0x80
00485 #define IRQ_TXDONE      0x40
00486 #define IRQ_FIFOP       0x20
00487 #define IRQ_SFD         0x10
00488 #define IRQ_CCA         0x08
00489 #define IRQ_CSP_WT      0x04
00490 #define IRQ_CSP_STOP    0x02
00491 #define IRQ_CSP_INT     0x01
00492 
00493 __sfr __at (0xEA)   T4CNT;
00494 __sfr __at (0xEB)   T4CTL;
00495 /*T4CTL bits*/
00496 #define T4DIV2  0x80
00497 #define T4DIV1  0x40
00498 #define T4DIV0  0x20
00499 #define T4START 0x10
00500 #define T4OVFIM 0x08
00501 #define T4CLR   0x04
00502 #define T4MODE1 0x02
00503 #define T4MODE0 0x01
00504 
00505 __sfr __at (0xEC)   T4CCTL0;
00506 /*T4CCTL0 bits*/
00507 #define T4IM    0x40
00508 #define T4CMP2  0x20
00509 #define T4CMP1  0x10
00510 #define T4CMP0  0x08
00511 #define T4MODE  0x04
00512 #define T4CAP1  0x02
00513 #define T4CAP0  0x01
00514 
00515 __sfr __at (0xED)   T4CC0;
00516 __sfr __at (0xEE)   T4CCTL1;
00517 /*T4CCTL0 bits apply*/
00518 __sfr __at (0xEF)   T4CC1;
00519 
00520 __sfr __at (0xF0) B    ;
00521 __sfr __at (0xF1)   PERCFG;
00522 /*PERCFG bits*/
00523 #define T1CFG   0x40
00524 #define T3CFG   0x20
00525 #define T4CFG   0x10
00526 #define U1CFG   0x02
00527 #define U0CFG   0x01
00528 
00529 __sfr __at (0xF2)   ADCCFG;
00530 /*ADCCFG bits*/
00531 #define ADC7EN  0x80
00532 #define ADC6EN  0x40
00533 #define ADC5EN  0x20
00534 #define ADC4EN  0x10
00535 #define ADC3EN  0x08
00536 #define ADC2EN  0x04
00537 #define ADC1EN  0x02
00538 #define ADC0EN  0x01
00539 
00540 __sfr __at (0xF3)   P0SEL;
00541 __sfr __at (0xF4)   P1SEL;
00542 __sfr __at (0xF5)   P2SEL;
00543 /*P2SEL bits*/
00544 #define PRI3P1  0x40
00545 #define PRI2P1  0x20
00546 #define PRI1P1  0x10
00547 #define PRI0P1  0x08
00548 #define SELP2_4 0x04
00549 #define SELP2_3 0x02
00550 #define SELP2_0 0x01
00551 
00552 __sfr __at (0xF6)   P1INP;
00553 
00554 __sfr __at (0xF7)   P2INP;
00555 /*P2INP bits*/
00556 #define PDUP2   0x80
00557 #define PDUP1   0x40
00558 #define PDUP0   0x20
00559 #define MDP2_4  0x10
00560 #define MDP2_3  0x08
00561 #define MDP2_2  0x04
00562 #define MDP2_1  0x02
00563 #define MDP2_0  0x01
00564 
00565 __sfr __at (0xF8)   U1CSR;
00566 __sfr __at (0xF9)   U1BUF;
00567 __sfr __at (0xFA)   U1BAUD;
00568 __sfr __at (0xFB)   U1UCR;
00569 __sfr __at (0xFC)   U1GCR;
00570 __sfr __at (0xFD)   P0DIR;
00571 __sfr __at (0xFE)   P1DIR;
00572 
00573 __sfr __at (0xFF)   P2DIR;
00574 /*P2DIR bits*/
00575 #define PRI1P0  0x80
00576 #define PRI0P0  0x40
00577 #define DIRP2_4 0x10
00578 #define DIRP2_3 0x08
00579 #define DIRP2_2 0x04
00580 #define DIRP2_1 0x02
00581 #define DIRP2_0 0x01
00582 
00583 /*  IEN0  */
00584 /*__sbit __at (0xA8) EA   ;
00585 __sbit __at (0x99) TI   ;
00586 __sbit __at (0x9A) RB8  ;
00587 __sbit __at (0x9B) TB8  ;
00588 __sbit __at (0x9C) REN  ;
00589 __sbit __at (0x9D) SM2  ;
00590 __sbit __at (0x9E) SM1  ;
00591 __sbit __at (0x9F) SM0  ;*/
00592 
00593 
00594 
00595 /* Interrupt numbers: address = (number * 8) + 3 */
00596 /*#undef IE0_VECTOR
00597 #undef TF0_VECTOR
00598 #undef IE1_VECTOR
00599 #undef TF1_VECTOR
00600 #undef SI0_VECTOR*/
00601 
00602 /* CC2430 interrupt vectors */
00603 #define RFERR_VECTOR    0
00604 #define ADC_VECTOR      1
00605 #define URX0_VECTOR     2
00606 #define URX1_VECTOR     3
00607 #define ENC_VECTOR      4
00608 #define ST_VECTOR       5
00609 #define P2INT_VECTOR    6
00610 #define UTX0_VECTOR     7
00611 #define DMA_VECTOR      8
00612 #define T1_VECTOR       9
00613 #define T2_VECTOR       10
00614 #define T3_VECTOR       11
00615 #define T4_VECTOR       12
00616 #define P0INT_VECTOR    13
00617 #define UTX1_VECTOR     14
00618 #define P1INT_VECTOR    15
00619 #define RF_VECTOR       16
00620 #define WDT_VECTOR      17
00621 
00622 /* RF control registers*/
00623 __xdata __at (0xDF02) unsigned char MDMCTRL0H;
00624 __xdata __at (0xDF03) unsigned char MDMCTRL0L;
00625 __xdata __at (0xDF04) unsigned char MDMCTRL1H;
00626 __xdata __at (0xDF05) unsigned char MDMCTRL1L;
00627 __xdata __at (0xDF06) unsigned char RSSIH;
00628 __xdata __at (0xDF07) unsigned char RSSIL;
00629 __xdata __at (0xDF08) unsigned char SYNCWORDH;
00630 __xdata __at (0xDF09) unsigned char SYNCWORDL;
00631 __xdata __at (0xDF0A) unsigned char TXCTRLH;
00632 __xdata __at (0xDF0B) unsigned char TXCTRLL;
00633 __xdata __at (0xDF0C) unsigned char RXCTRL0H;
00634 __xdata __at (0xDF0D) unsigned char RXCTRL0L;
00635 __xdata __at (0xDF0E) unsigned char RXCTRL1H;
00636 __xdata __at (0xDF0F) unsigned char RXCTRL1L;
00637 __xdata __at (0xDF10) unsigned char FSCTRLH;
00638 __xdata __at (0xDF11) unsigned char FSCTRLL;
00639 __xdata __at (0xDF12) unsigned char CSPX;
00640 __xdata __at (0xDF13) unsigned char CSPY;
00641 __xdata __at (0xDF14) unsigned char CSPZ;
00642 __xdata __at (0xDF15) unsigned char CSPCTRL;
00643 __xdata __at (0xDF16) unsigned char CSPT;
00644 __xdata __at (0xDF17) unsigned char RFPWR;
00645 #define ADI_RADIO_PD    0x10
00646 #define RREG_RADIO_PD   0x08
00647 #define RREG_DELAY_MASK 0x07
00648 
00649 __xdata __at (0xDF20) unsigned char FSMTCH;
00650 __xdata __at (0xDF21) unsigned char FSMTCL;
00651 __xdata __at (0xDF22) unsigned char MANANDH;
00652 __xdata __at (0xDF23) unsigned char MANANDL;
00653 __xdata __at (0xDF24) unsigned char MANORH;
00654 __xdata __at (0xDF25) unsigned char MANORL;
00655 __xdata __at (0xDF26) unsigned char AGCCTRLH;
00656 __xdata __at (0xDF27) unsigned char AGCCTRLL;
00657 
00658 __xdata __at (0xDF39) unsigned char FSMSTATE;
00659 __xdata __at (0xDF3A) unsigned char ADCTSTH;
00660 __xdata __at (0xDF3B) unsigned char ADCTSTL;
00661 __xdata __at (0xDF3C) unsigned char DACTSTH;
00662 __xdata __at (0xDF3D) unsigned char DACTSTL;
00663 
00664 __xdata __at (0xDF43) unsigned char IEEE_ADDR0;
00665 __xdata __at (0xDF44) unsigned char IEEE_ADDR1;
00666 __xdata __at (0xDF45) unsigned char IEEE_ADDR2;
00667 __xdata __at (0xDF46) unsigned char IEEE_ADDR3;
00668 __xdata __at (0xDF47) unsigned char IEEE_ADDR4;
00669 __xdata __at (0xDF48) unsigned char IEEE_ADDR5;
00670 __xdata __at (0xDF49) unsigned char IEEE_ADDR6;
00671 __xdata __at (0xDF4A) unsigned char IEEE_ADDR7;
00672 __xdata __at (0xDF4B) unsigned char PANIDH;
00673 __xdata __at (0xDF4C) unsigned char PANIDL;
00674 __xdata __at (0xDF4D) unsigned char SHORTADDRH;
00675 __xdata __at (0xDF4E) unsigned char SHORTADDRL;
00676 __xdata __at (0xDF4F) unsigned char IOCFG0;
00677 __xdata __at (0xDF50) unsigned char IOCFG1;
00678 __xdata __at (0xDF51) unsigned char IOCFG2;
00679 __xdata __at (0xDF52) unsigned char IOCFG3;
00680 __xdata __at (0xDF53) unsigned char RXFIFOCNT;
00681 __xdata __at (0xDF54) unsigned char FSMTC1;
00682 #define ABORTRX_ON_SRXON 0x20
00683 #define RX_INTERRUPTED  0x10
00684 #define AUTO_TX2RX_OFF  0x08
00685 #define RX2RX_TIME_OFF  0x04
00686 #define PENDING_OR      0x02
00687 #define ACCEPT_ACKPKT   0x01
00688 
00689 __xdata __at (0xDF60) unsigned char CHVER;
00690 __xdata __at (0xDF61) unsigned char CHIPID;
00691 __xdata __at (0xDF62) unsigned char RFSTATUS;
00692 #define TX_ACTIVE       0x10
00693 #define FIFO            0x08
00694 #define FIFOP           0x04
00695 #define SFD             0x02
00696 #define CCA             0x01
00697 
00698 __xdata __at (0xDFC1) unsigned char   U0BUF_SHADOW;
00699 
00700 __xdata __at (0xDFD9) unsigned char RFD_SHADOW;
00701 
00702 __xdata __at (0xDFF9) unsigned char U1BUF_SHADOW;
00703 
00704 __xdata __at (0xDFBA) unsigned int ADC_SHADOW;
00705 
00706 #endif /*REG_CC2430*/