default_lowlevel.c

00001 /*
00002  * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
00003  * to the MC1322x project (http://mc1322x.devl.org)
00004  * All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the Institute nor the names of its contributors
00015  *    may be used to endorse or promote products derived from this software
00016  *    without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
00019  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00021  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
00022  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00023  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00024  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00025  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00026  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00027  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * This file is part of libmc1322x: see http://mc1322x.devl.org
00031  * for details. 
00032  *
00033  *
00034  */
00035 
00036 #include <mc1322x.h>
00037 #include <stdint.h>
00038 
00039 void default_vreg_init(void) {
00040         volatile uint32_t i;
00041         *CRM_SYS_CNTL = 0x00000018; /* set default state */
00042         *CRM_VREG_CNTL = 0x00000f04; /* bypass the buck */
00043         for(i=0; i<0x161a8; i++) { continue; } /* wait for the bypass to take */
00044 //      while((((*(volatile uint32_t *)(0x80003018))>>17) & 1) !=1) { continue; } /* wait for the bypass to take */
00045         *CRM_VREG_CNTL = 0x00000ff8; /* start the regulators */
00046 }
00047 
00048 void uart1_init(uint16_t inc, uint16_t mod, uint8_t samp) {
00049                 
00050         /* UART must be disabled to set the baudrate */
00051         *UART1_UCON = 0;
00052         *UART1_UBRCNT = ( inc << 16 ) | mod; 
00053 
00054         /* TX and CTS as outputs */
00055         GPIO->PAD_DIR_SET.GPIO_14 = 1;
00056         GPIO->PAD_DIR_SET.GPIO_16 = 1;
00057 
00058         /* RX and RTS as inputs */
00059         GPIO->PAD_DIR_RESET.GPIO_15 = 1;
00060         GPIO->PAD_DIR_RESET.GPIO_17 = 1;
00061 
00062         /* see Section 11.5.1.2 Alternate Modes */
00063         /* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */
00064         /* From the datasheet: "The peripheral function will control operation of the pad IF */
00065         /* THE PERIPHERAL IS ENABLED. */
00066 
00067 #if UART1_RX_BUFFERSIZE > 32
00068         *UART1_UCON = (1 << 0) | (1 << 1) | (1 << 12); /* enable receive, transmit, both interrupts, flow control*/
00069         *UART1_URXCON = 30;                                     /* interrupt when fifo is nearly full */
00070         *UART1_UCTS   = 16;                             /* drop cts when interrupt can't push to RAM anymore */
00071         *GPIO_FUNC_SEL1 |= ( (0x01 << (0*2)) | (0x01 << (1*2)) ); /* set GPIO17-16 to UART1 CTS and RTS */
00072         
00073 //      *UART1_UCON = (1 << 0) | (1 << 1) ;     /* enable receive, transmit, and both interrupts */
00074 //      *UART1_URXCON = 30;                                     /* interrupt when fifo is nearly full */
00075         u1_rx_head = 0; u1_rx_tail = 0; u1_rx_hyst = 0;
00076 #elif UART1_RX_BUFFERSIZE < 32                  /* enable receive, transmit, flow control, disable rx interrupt */
00077         *UART1_UCON = (1 << 0) | (1 << 1) | (1 << 12) | (1 << 14); 
00078         *UART1_UCTS = UART1_RX_BUFFERSIZE;  /* drop cts when tx buffer at trigger level */
00079         *GPIO_FUNC_SEL1 = ( (0x01 << (0*2)) | (0x01 << (1*2)) ); /* set GPIO17-16 to UART1 CTS and RTS */
00080 #else 
00081         *UART1_UCON = (1 << 0) | (1 << 1) | (1 << 14); /* enable receive, transmit, disable rx interrupt */
00082 #endif
00083 
00084         if(samp == UCON_SAMP_16X) 
00085                 set_bit(*UART1_UCON,UCON_SAMP);
00086         *GPIO_FUNC_SEL0 = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/
00087 
00088         /* interrupt when there are this number or more bytes free in the TX buffer*/
00089         *UART1_UTXCON = 16;
00090     u1_tx_head = 0; u1_tx_tail = 0;
00091 
00092         /* enable UART1 interrupts in the interrupt controller */
00093         enable_irq(UART1);
00094 }

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