micro-common.c

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00001 /** @file micro-common.c
00002  *  @brief STM32W108 micro specific HAL functions common to 
00003  *  full and minimal hal
00004  *
00005  *
00006  * <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved.        -->
00007  */
00008 
00009 
00010 
00011 #include PLATFORM_HEADER
00012 #include BOARD_HEADER
00013 #include "error.h"
00014 #include "hal/micro/micro-common.h"
00015 #include "hal/micro/cortexm3/micro-common.h"
00016 
00017 void halInternalEnableWatchDog(void)
00018 {
00019   //Just to be on the safe side, restart the watchdog before enabling it
00020   WDOG_RESET = 1;
00021   WDOG_KEY = 0xEABE;
00022   WDOG_CFG = WDOG_ENABLE;
00023 }
00024 
00025 void halInternalResetWatchDog(void)
00026 {
00027   //Writing any value will restart the watchdog
00028   WDOG_RESET = 1;
00029 }
00030 
00031 void halInternalDisableWatchDog(int8u magicKey)
00032 {
00033   if (magicKey == MICRO_DISABLE_WATCH_DOG_KEY) {
00034     WDOG_KEY = 0xDEAD;
00035     WDOG_CFG = WDOG_DISABLE;
00036   }
00037 }
00038 
00039 boolean halInternalWatchDogEnabled(void)
00040 {
00041   if(WDOG_CFG&WDOG_ENABLE) {
00042     return TRUE;
00043   } else {
00044     return FALSE;
00045   }
00046 }
00047 
00048 void halGpioConfig(int32u io, int32u config)
00049 {
00050   static volatile int32u *const configRegs[] = 
00051     { (volatile int32u *)GPIO_PACFGL_ADDR,
00052       (volatile int32u *)GPIO_PACFGH_ADDR,
00053       (volatile int32u *)GPIO_PBCFGL_ADDR,
00054       (volatile int32u *)GPIO_PBCFGH_ADDR,
00055       (volatile int32u *)GPIO_PCCFGL_ADDR,
00056       (volatile int32u *)GPIO_PCCFGH_ADDR };
00057   int32u portcfg;
00058   portcfg = *configRegs[io/4];                // get current config                   
00059   portcfg = portcfg & ~((0xF)<<((io&3)*4));   // mask out config of this pin
00060   *configRegs[io/4] = portcfg | (config <<((io&3)*4));
00061 }
00062 
00063 void halGpioSet(int32u gpio, boolean value)
00064 {
00065   if(gpio/8 < 3) {
00066     if (value) {
00067       *((volatile int32u *)(GPIO_PxSET_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7);
00068     } else {
00069       *((volatile int32u *)(GPIO_PxCLR_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7);
00070     }
00071   }
00072 }
00073 
00074 int16u halInternalStartSystemTimer(void)
00075 {
00076   //Since the SleepTMR is the only timer maintained during deep sleep, it is
00077   //used as the System Timer (RTC).  We maintain a 32 bit hardware timer
00078   //configured for a tick value time of 1024 ticks/second (0.9765625 ms/tick)
00079   //using either the 10 kHz internal SlowRC clock divided and calibrated to
00080   //1024 Hz or the external 32.768 kHz crystal divided to 1024 Hz.
00081   //With a tick time of ~1ms, this 32bit timer will wrap after ~48.5 days.
00082   
00083   //disable top-level interrupt while configuring
00084   INT_CFGCLR = INT_SLEEPTMR;
00085   
00086   #ifdef ENABLE_OSC32K
00087     #ifdef DIGITAL_OSC32_EXT
00088       //Disable both OSC32K and SLOWRC if using external digital clock input
00089       SLEEPTMR_CLKEN = 0;
00090     #else//!DIGITAL_OSC32_EXT
00091       //Enable the 32kHz XTAL (and disable SlowRC since it is not needed)
00092       SLEEPTMR_CLKEN = SLEEPTMR_CLK32KEN;
00093     #endif
00094     //Sleep timer configuration is the same for crystal and external clock
00095     SLEEPTMR_CFG = (SLEEPTMR_ENABLE            | //enable TMR
00096                    (0 << SLEEPTMR_DBGPAUSE_BIT)| //TMR paused when halted
00097                    (5 << SLEEPTMR_CLKDIV_BIT)  | //divide down to 1024Hz
00098                    (1 << SLEEPTMR_CLKSEL_BIT)) ; //select XTAL
00099   #else //!ENABLE_OSC32K
00100     //Enable the SlowRC (and disable 32kHz XTAL since it is not needed)
00101     SLEEPTMR_CLKEN = SLEEPTMR_CLK10KEN;
00102     SLEEPTMR_CFG = (SLEEPTMR_ENABLE            | //enable TMR
00103                    (0 << SLEEPTMR_DBGPAUSE_BIT)| //TMR paused when halted
00104                    (0 << SLEEPTMR_CLKDIV_BIT)  | //already 1024Hz
00105                    (0 << SLEEPTMR_CLKSEL_BIT)) ; //select SlowRC
00106     #ifndef DISABLE_RC_CALIBRATION
00107       halInternalCalibrateSlowRc(); //calibrate SlowRC to 1024Hz
00108     #endif//DISABLE_RC_CALIBRATION
00109   #endif//ENABLE_OSC32K
00110   
00111   //clear out any stale interrupts
00112   INT_SLEEPTMRFLAG = (INT_SLEEPTMRWRAP | INT_SLEEPTMRCMPA | INT_SLEEPTMRCMPB);
00113   //turn off second level interrupts.  they will be enabled elsewhere as needed
00114   INT_SLEEPTMRCFG = INT_SLEEPTMRCFG_RESET;
00115   //enable top-level interrupt
00116   INT_CFGSET = INT_SLEEPTMR;
00117   
00118   return 0;
00119 }
00120 
00121 

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