00001 /* 00002 * Copyright (c) 2007, Swedish Institute of Computer Science 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without 00006 * modification, are permitted provided that the following conditions 00007 * are met: 00008 * 1. Redistributions of source code must retain the above copyright 00009 * notice, this list of conditions and the following disclaimer. 00010 * 2. Redistributions in binary form must reproduce the above copyright 00011 * notice, this list of conditions and the following disclaimer in the 00012 * documentation and/or other materials provided with the distribution. 00013 * 3. Neither the name of the Institute nor the names of its contributors 00014 * may be used to endorse or promote products derived from this software 00015 * without specific prior written permission. 00016 * 00017 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 00018 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00019 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00020 * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 00021 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00022 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 00023 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 00024 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00025 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00026 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00027 * SUCH DAMAGE. 00028 * 00029 * @(#)$Id: cb_uart01.c,v 1.1 2007/02/02 14:09:06 bg- Exp $ 00030 */ 00031 00032 #include <stdio.h> 00033 00034 #include <avr/interrupt.h> 00035 00036 #include "contiki.h" 00037 00038 #include "dev/slip.h" 00039 00040 static int 00041 uart0_putchar(char c, FILE *stream) 00042 { 00043 while (!(UCSR0A & BV(UDRE0))) 00044 ; 00045 UDR0 = c; 00046 00047 return c; 00048 } 00049 00050 static FILE uart0_stdout = 00051 FDEV_SETUP_STREAM(uart0_putchar, NULL, _FDEV_SETUP_WRITE); 00052 00053 void 00054 slip_arch_init(unsigned long ubr) 00055 { 00056 u8_t dummy; 00057 spl_t s = splhigh(); 00058 00059 UBRR1L = ubr; 00060 UBRR1H = ubr >> 8; 00061 00062 UCSR1C = BV(UCSZ1) | BV(UCSZ0); /* 1 start bit, no parity, 1 stop bit */ 00063 UCSR1B = BV(RXEN) | BV(TXEN) | BV(RXCIE); 00064 dummy = UDR1; /* Flush RX buffer. */ 00065 00066 /* And now UART0. */ 00067 UBRR0L = BAUD2UBR(38400); 00068 UBRR0H = BAUD2UBR(38400) >> 8; 00069 00070 UCSR0C = BV(UCSZ1) | BV(UCSZ0); /* 1 start bit, no parity, 1 stop bit */ 00071 UCSR0B = BV(TXEN); /* TX ONLY!!! */ 00072 00073 splx(s); 00074 00075 stdout = &uart0_stdout; 00076 } 00077 00078 void 00079 slip_arch_writeb(unsigned char c) 00080 { 00081 while (!(UCSR1A & BV(UDRE1))) 00082 ; 00083 UDR1 = c; 00084 } 00085 00086 ISR(SIG_UART1_RECV) 00087 { 00088 /* Should deal with receive errors. */ 00089 slip_input_byte(UDR1); 00090 }