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00058 #include "config.h"
00059 #include "storage/ctrl_access.h"
00060 #include "avr_flash.h"
00061
00062
00063
00064
00065 #if (ACCESS_MEM_TO_MEM == ENABLED)
00066 #include "modules/file_system/fat.h"
00067 U8 buf_sector[FS_SIZE_OF_SECTOR];
00068 #endif
00069
00070
00071
00072
00073
00074
00075
00076
00077 #ifndef LUN_0
00078 # error LUN_0 must be defined with ENABLE or DISABLE in conf_access.h
00079 #endif
00080 #ifndef LUN_1
00081 # error LUN_1 must be defined with ENABLE or DISABLE in conf_access.h
00082 #endif
00083 #ifndef LUN_2
00084 # error LUN_2 must be defined with ENABLE or DISABLE in conf_access.h
00085 #endif
00086 #ifndef LUN_3
00087 # error LUN_3 must be defined with ENABLE or DISABLE in conf_access.h
00088 #endif
00089 #ifndef LUN_4
00090 # error LUN_4 must be defined with ENABLE or DISABLE in conf_access.h
00091 #endif
00092 #ifndef LUN_5
00093 # error LUN_5 must be defined with ENABLE or DISABLE in conf_access.h
00094 #endif
00095 #ifndef LUN_6
00096 # error LUN_6 must be defined with ENABLE or DISABLE in conf_access.h
00097 #endif
00098 #ifndef LUN_7
00099 # error LUN_7 must be defined with ENABLE or DISABLE in conf_access.h
00100 #endif
00101 #ifndef LUN_USB
00102 # error LUN_USB must be defined with ENABLE or DISABLE in conf_access.h
00103 #endif
00104
00105
00106
00107 #if (LUN_0 == ENABLE)
00108 #define LUN_0_EN 1
00109 U8 FLASH lun0_name[]=LUN_0_NAME;
00110 #else
00111 #define LUN_0_EN 0
00112 #endif
00113 #if (LUN_1 == ENABLE)
00114 #define LUN_1_EN 1
00115 U8 FLASH lun1_name[]=LUN_1_NAME;
00116 #else
00117 #define LUN_1_EN 0
00118 #endif
00119 #if (LUN_2 == ENABLE)
00120 #define LUN_2_EN 1
00121 U8 FLASH lun2_name[]=LUN_2_NAME;
00122 #else
00123 #define LUN_2_EN 0
00124 #endif
00125 #if (LUN_3 == ENABLE)
00126 #define LUN_3_EN 1
00127 U8 FLASH lun3_name[]=LUN_3_NAME;
00128 #else
00129 #define LUN_3_EN 0
00130 #endif
00131 #if (LUN_4 == ENABLE)
00132 #define LUN_4_EN 1
00133 U8 FLASH lun4_name[]=LUN_4_NAME;
00134 #else
00135 #define LUN_4_EN 0
00136 #endif
00137 #if (LUN_5 == ENABLE)
00138 #define LUN_5_EN 1
00139 U8 FLASH lun5_name[]=LUN_5_NAME;
00140 #else
00141 #define LUN_5_EN 0
00142 #endif
00143 #if (LUN_6 == ENABLE)
00144 #define LUN_6_EN 1
00145 U8 FLASH lun6_name[]=LUN_6_NAME;
00146 #else
00147 #define LUN_6_EN 0
00148 #endif
00149 #if (LUN_7 == ENABLE)
00150 #define LUN_7_EN 1
00151 U8 FLASH lun7_name[]=LUN_7_NAME;
00152 #else
00153 #define LUN_7_EN 0
00154 #endif
00155 #if (LUN_USB == ENABLE)
00156 #define LUN_USB_EN 1
00157 U8 FLASH lunusb_name[]=LUN_USB_NAME;
00158 #else
00159 #define LUN_USB_EN 0
00160 #endif
00161
00162
00163 #define LUN_ID_0 (0)
00164 #define LUN_ID_1 (LUN_0_EN)
00165 #define LUN_ID_2 (LUN_0_EN+LUN_1_EN)
00166 #define LUN_ID_3 (LUN_0_EN+LUN_1_EN+LUN_2_EN)
00167 #define LUN_ID_4 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN)
00168 #define LUN_ID_5 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN)
00169 #define LUN_ID_6 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN+LUN_5_EN)
00170 #define LUN_ID_7 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN+LUN_5_EN+LUN_6_EN)
00171 #define MAX_LUN (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN+LUN_5_EN+LUN_6_EN+LUN_7_EN)
00172 #define LUN_ID_USB (MAX_LUN)
00173
00174
00175 #if (MAX_LUN == 0)
00176 #error No memory is active in conf_access.h
00177 #endif
00178
00179
00180 #if (GLOBAL_WR_PROTECT == ENABLED)
00181 static U8 g_u8_wr_protect;
00182 #endif
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192 U8 get_nb_lun()
00193 {
00194 #if (MEM_USB == ENABLED)
00195 return (MAX_LUN + Host_getlun());
00196 #else
00197 return MAX_LUN;
00198 #endif
00199 }
00200
00201
00202
00203
00204
00205
00206 U8 get_cur_lun()
00207 {
00208 return 0;
00209 }
00210
00211
00212
00213
00214
00215
00216
00217
00218
00219
00220
00221
00222
00223
00224
00225 Ctrl_status mem_test_unit_ready( U8 lun )
00226 {
00227 switch( lun )
00228 {
00229 # if (LUN_0 == ENABLE)
00230 case LUN_ID_0:
00231 return Lun_0_test_unit_ready();
00232 break;
00233 # endif
00234 # if (LUN_1 == ENABLE)
00235 case LUN_ID_1:
00236 return Lun_1_test_unit_ready();
00237 break;
00238 # endif
00239 # if (LUN_2 == ENABLE)
00240 case LUN_ID_2:
00241 return Lun_2_test_unit_ready();
00242 break;
00243 # endif
00244 # if (LUN_3 == ENABLE)
00245 case LUN_ID_3:
00246 return Lun_3_test_unit_ready();
00247 break;
00248 # endif
00249 # if (LUN_4 == ENABLE)
00250 case LUN_ID_4:
00251 return Lun_4_test_unit_ready();
00252 break;
00253 # endif
00254 # if (LUN_5 == ENABLE)
00255 case LUN_ID_5:
00256 return Lun_5_test_unit_ready();
00257 break;
00258 # endif
00259 # if (LUN_6 == ENABLE)
00260 case LUN_ID_6:
00261 return Lun_6_test_unit_ready();
00262 break;
00263 # endif
00264 # if (LUN_7 == ENABLE)
00265 case LUN_ID_7:
00266 return Lun_7_test_unit_ready();
00267 break;
00268 # endif
00269 # if (LUN_USB == ENABLE)
00270 default:
00271 return Lun_usb_test_unit_ready(lun - LUN_ID_USB);
00272 break;
00273 # endif
00274 }
00275 return CTRL_FAIL;
00276 }
00277
00278
00279
00280
00281
00282
00283
00284
00285
00286
00287
00288 Ctrl_status mem_read_capacity( U8 lun , U32 _MEM_TYPE_SLOW_ *u32_nb_sector )
00289 {
00290 switch( lun )
00291 {
00292 # if (LUN_0 == ENABLE)
00293 case LUN_ID_0:
00294 return Lun_0_read_capacity( u32_nb_sector );
00295 break;
00296 # endif
00297 # if (LUN_1 == ENABLE)
00298 case LUN_ID_1:
00299 return Lun_1_read_capacity( u32_nb_sector );
00300 break;
00301 # endif
00302 # if (LUN_2 == ENABLE)
00303 case LUN_ID_2:
00304 return Lun_2_read_capacity( u32_nb_sector );
00305 break;
00306 # endif
00307 # if (LUN_3 == ENABLE)
00308 case LUN_ID_3:
00309 return Lun_3_read_capacity( u32_nb_sector );
00310 break;
00311 # endif
00312 # if (LUN_4 == ENABLE)
00313 case LUN_ID_4:
00314 return Lun_4_read_capacity( u32_nb_sector );
00315 break;
00316 # endif
00317 # if (LUN_5 == ENABLE)
00318 case LUN_ID_5:
00319 return Lun_5_read_capacity( u32_nb_sector );
00320 break;
00321 # endif
00322 # if (LUN_6 == ENABLE)
00323 case LUN_ID_6:
00324 return Lun_6_read_capacity( u32_nb_sector );
00325 break;
00326 # endif
00327 # if (LUN_7 == ENABLE)
00328 case LUN_ID_7:
00329 return Lun_7_read_capacity( u32_nb_sector );
00330 break;
00331 # endif
00332 # if (LUN_USB == ENABLE)
00333 default:
00334 return Lun_usb_read_capacity( lun - LUN_ID_USB,u32_nb_sector );
00335 break;
00336 # endif
00337 }
00338 return CTRL_FAIL;
00339 }
00340
00341
00342
00343
00344
00345
00346
00347
00348
00349
00350 Bool mem_wr_protect( U8 lun )
00351 {
00352 switch( lun )
00353 {
00354 # if (LUN_0 == ENABLE)
00355 case LUN_ID_0:
00356 return Lun_0_wr_protect();
00357 break;
00358 # endif
00359 # if (LUN_1 == ENABLE)
00360 case LUN_ID_1:
00361 return Lun_1_wr_protect();
00362 break;
00363 # endif
00364 # if (LUN_2 == ENABLE)
00365 case LUN_ID_2:
00366 return Lun_2_wr_protect();
00367 break;
00368 # endif
00369 # if (LUN_3 == ENABLE)
00370 case LUN_ID_3:
00371 return Lun_3_wr_protect();
00372 break;
00373 # endif
00374 # if (LUN_4 == ENABLE)
00375 case LUN_ID_4:
00376 return Lun_4_wr_protect();
00377 break;
00378 # endif
00379 # if (LUN_5 == ENABLE)
00380 case LUN_ID_5:
00381 return Lun_5_wr_protect();
00382 break;
00383 # endif
00384 # if (LUN_6 == ENABLE)
00385 case LUN_ID_6:
00386 return Lun_6_wr_protect();
00387 break;
00388 # endif
00389 # if (LUN_7 == ENABLE)
00390 case LUN_ID_7:
00391 return Lun_7_wr_protect();
00392 break;
00393 # endif
00394 # if (LUN_USB == ENABLE)
00395 default:
00396 return Lun_usb_wr_protect(lun - LUN_ID_USB);
00397 break;
00398 # endif
00399 }
00400 return CTRL_FAIL;
00401 }
00402
00403
00404
00405
00406
00407
00408
00409
00410 Bool mem_removal( U8 lun )
00411 {
00412 switch( lun )
00413 {
00414 # if (LUN_0 == ENABLE)
00415 case LUN_ID_0:
00416 return Lun_0_removal();
00417 break;
00418 # endif
00419 # if (LUN_1 == ENABLE)
00420 case LUN_ID_1:
00421 return Lun_1_removal();
00422 break;
00423 # endif
00424 # if (LUN_2 == ENABLE)
00425 case LUN_ID_2:
00426 return Lun_2_removal();
00427 break;
00428 # endif
00429 # if (LUN_3 == ENABLE)
00430 case LUN_ID_3:
00431 return Lun_3_removal();
00432 break;
00433 # endif
00434 # if (LUN_4 == ENABLE)
00435 case LUN_ID_4:
00436 return Lun_4_removal();
00437 break;
00438 # endif
00439 # if (LUN_5 == ENABLE)
00440 case LUN_ID_5:
00441 return Lun_5_removal();
00442 break;
00443 # endif
00444 # if (LUN_6 == ENABLE)
00445 case LUN_ID_6:
00446 return Lun_6_removal();
00447 break;
00448 # endif
00449 # if (LUN_7 == ENABLE)
00450 case LUN_ID_7:
00451 return Lun_7_removal();
00452 break;
00453 # endif
00454 # if (LUN_USB == ENABLE)
00455 default:
00456 return Lun_usb_removal();
00457 break;
00458 # endif
00459 }
00460 return CTRL_FAIL;
00461 }
00462
00463
00464
00465
00466
00467
00468
00469 #if 0 //not used anywhere and the FLASH attribute causes a compilation warning - dak
00470 U8 FLASH* mem_name( U8 lun )
00471 {
00472 switch( lun )
00473 {
00474 # if (LUN_0 == ENABLE)
00475 case LUN_ID_0:
00476 return (U8 FLASH*)lun0_name;
00477 break;
00478 # endif
00479 # if (LUN_1 == ENABLE)
00480 case LUN_ID_1:
00481 return (U8 FLASH*)lun1_name;
00482 break;
00483 # endif
00484 # if (LUN_2 == ENABLE)
00485 case LUN_ID_2:
00486 return (U8 FLASH*)lun2_name;
00487 break;
00488 # endif
00489 # if (LUN_3 == ENABLE)
00490 case LUN_ID_3:
00491 return (U8 FLASH*)lun3_name;
00492 break;
00493 # endif
00494 # if (LUN_4 == ENABLE)
00495 case LUN_ID_4:
00496 return (U8 FLASH*)lun4_name;
00497 break;
00498 # endif
00499 # if (LUN_5 == ENABLE)
00500 case LUN_ID_5:
00501 return (U8 FLASH*)lun5_name;
00502 break;
00503 # endif
00504 # if (LUN_6 == ENABLE)
00505 case LUN_ID_6:
00506 return (U8 FLASH*)lun6_name;
00507 break;
00508 # endif
00509 # if (LUN_7 == ENABLE)
00510 case LUN_ID_7:
00511 return (U8 FLASH*)lun7_name;
00512 break;
00513 # endif
00514 # if (LUN_USB == ENABLE)
00515 default:
00516 return (U8 FLASH*)lunusb_name;
00517 break;
00518 # endif
00519 }
00520 return 0;
00521 }
00522 #endif
00523
00524
00525
00526
00527
00528
00529
00530
00531
00532
00533
00534
00535
00536
00537
00538
00539
00540 Ctrl_status memory_2_usb( U8 lun , U32 addr , U16 nb_sector )
00541 {
00542 Ctrl_status status=0;
00543
00544 switch( lun )
00545 {
00546 # if (LUN_0 == ENABLE)
00547 case LUN_ID_0:
00548 status = Lun_0_read_10(addr , nb_sector);
00549 if (CTRL_GOOD == status)
00550 {
00551 status = Lun_0_usb_read();
00552 }
00553 break;
00554 # endif
00555 # if (LUN_1 == ENABLE)
00556 case LUN_ID_1:
00557 status = Lun_1_read_10(addr , nb_sector);
00558 if (CTRL_GOOD == status)
00559 {
00560 status = Lun_1_usb_read();
00561 }
00562 break;
00563 # endif
00564 # if (LUN_2 == ENABLE)
00565 case LUN_ID_2:
00566 status = Lun_2_read_10(addr , nb_sector);
00567 if (CTRL_GOOD == status)
00568 {
00569 status = Lun_2_usb_read();
00570 }
00571 break;
00572 # endif
00573 # if (LUN_3 == ENABLE)
00574 case LUN_ID_3:
00575 status = Lun_3_read_10(addr , nb_sector);
00576 if (CTRL_GOOD == status)
00577 {
00578 status = Lun_3_usb_read();
00579 }
00580 break;
00581 # endif
00582 # if (LUN_4 == ENABLE)
00583 case LUN_ID_4:
00584 status = Lun_4_read_10(addr , nb_sector);
00585 if (CTRL_GOOD == status)
00586 {
00587 status = Lun_4_usb_read();
00588 }
00589 break;
00590 # endif
00591 # if (LUN_5 == ENABLE)
00592 case LUN_ID_5:
00593 status = Lun_5_read_10(addr , nb_sector);
00594 if (CTRL_GOOD == status)
00595 {
00596 status = Lun_5_usb_read();
00597 }
00598 break;
00599 # endif
00600 # if (LUN_6 == ENABLE)
00601 case LUN_ID_6:
00602 status = Lun_6_read_10(addr , nb_sector);
00603 if (CTRL_GOOD == status)
00604 {
00605 status = Lun_6_usb_read();
00606 }
00607 break;
00608 # endif
00609 # if (LUN_7 == ENABLE)
00610 case LUN_ID_7:
00611 status = Lun_7_read_10(addr , nb_sector);
00612 if (CTRL_GOOD == status)
00613 {
00614 status = Lun_7_usb_read();
00615 }
00616 break;
00617 # endif
00618 }
00619 return status;
00620 }
00621
00622
00623
00624
00625
00626
00627
00628
00629
00630
00631
00632
00633 Ctrl_status usb_2_memory( U8 lun , U32 addr , U16 nb_sector )
00634 {
00635 Ctrl_status status=0;
00636
00637 switch( lun )
00638 {
00639 # if (LUN_0 == ENABLE)
00640 case LUN_ID_0:
00641 status = Lun_0_write_10(addr , nb_sector);
00642 if (CTRL_GOOD == status)
00643 {
00644 status = Lun_0_usb_write();
00645 }
00646 break;
00647 # endif
00648 # if (LUN_1 == ENABLE)
00649 case LUN_ID_1:
00650 status = Lun_1_write_10(addr , nb_sector);
00651 if (CTRL_GOOD == status)
00652 {
00653 status = Lun_1_usb_write();
00654 }
00655 break;
00656 # endif
00657 # if (LUN_2 == ENABLE)
00658 case LUN_ID_2:
00659 status = Lun_2_write_10(addr , nb_sector);
00660 if (CTRL_GOOD == status)
00661 {
00662 status = Lun_2_usb_write();
00663 }
00664 break;
00665 # endif
00666 # if (LUN_3 == ENABLE)
00667 case LUN_ID_3:
00668 status = Lun_3_write_10(addr , nb_sector);
00669 if (CTRL_GOOD == status)
00670 {
00671 status = Lun_3_usb_write();
00672 }
00673 break;
00674 # endif
00675 # if (LUN_4 == ENABLE)
00676 case LUN_ID_4:
00677 status = Lun_4_write_10(addr , nb_sector);
00678 if (CTRL_GOOD == status)
00679 {
00680 status = Lun_4_usb_write();
00681 }
00682 break;
00683 # endif
00684 # if (LUN_5 == ENABLE)
00685 case LUN_ID_5:
00686 status = Lun_5_write_10(addr , nb_sector);
00687 if (CTRL_GOOD == status)
00688 {
00689 status = Lun_5_usb_write();
00690 }
00691 break;
00692 # endif
00693 # if (LUN_6 == ENABLE)
00694 case LUN_ID_6:
00695 status = Lun_6_write_10(addr , nb_sector);
00696 if (CTRL_GOOD == status)
00697 {
00698 status = Lun_6_usb_write();
00699 }
00700 break;
00701 # endif
00702 # if (LUN_7 == ENABLE)
00703 case LUN_ID_7:
00704 status = Lun_7_write_10(addr , nb_sector);
00705 if (CTRL_GOOD == status)
00706 {
00707 status = Lun_7_usb_write();
00708 }
00709 break;
00710 # endif
00711 }
00712 return status;
00713 }
00714
00715
00716 #if (ACCESS_MEM_TO_RAM == ENABLED)
00717
00718
00719
00720
00721
00722
00723
00724
00725
00726 Ctrl_status memory_2_ram( U8 lun , const U32 _MEM_TYPE_SLOW_ *addr , U8 _MEM_TYPE_SLOW_ *ram )
00727 {
00728
00729 Ctrl_status status;
00730
00731 switch( lun )
00732 {
00733 # if (LUN_0 == ENABLE)
00734 case LUN_ID_0:
00735 status = Lun_0_mem_2_ram(*addr , ram);
00736 if (CTRL_GOOD == status)
00737 {
00738 status = Lun_0_mem_2_ram_read();
00739 }
00740 break;
00741 # endif
00742 # if (LUN_1 == ENABLE)
00743 case LUN_ID_1:
00744 status = Lun_1_mem_2_ram(*addr , ram);
00745 if (CTRL_GOOD == status)
00746 {
00747 status = Lun_1_mem_2_ram_read();
00748 }
00749 break;
00750 # endif
00751 # if (LUN_2 == ENABLE)
00752 case LUN_ID_2:
00753 status = Lun_2_mem_2_ram(*addr , ram);
00754 if (CTRL_GOOD == status)
00755 {
00756 status = Lun_2_mem_2_ram_read();
00757 }
00758 break;
00759 # endif
00760 # if (LUN_3 == ENABLE)
00761 case LUN_ID_3:
00762 status = Lun_3_mem_2_ram(*addr , ram);
00763 if (CTRL_GOOD == status)
00764 {
00765 status = Lun_3_mem_2_ram_read();
00766 }
00767 break;
00768 # endif
00769 # if (LUN_4 == ENABLE)
00770 case LUN_ID_4:
00771 status = Lun_4_mem_2_ram(*addr , ram);
00772 if (CTRL_GOOD == status)
00773 {
00774 status = Lun_4_mem_2_ram_read();
00775 }
00776 break;
00777 # endif
00778 # if (LUN_5 == ENABLE)
00779 case LUN_ID_5:
00780 status = Lun_5_mem_2_ram(*addr , ram);
00781 if (CTRL_GOOD == status)
00782 {
00783 status = Lun_5_mem_2_ram_read();
00784 }
00785 break;
00786 # endif
00787 # if (LUN_6 == ENABLE)
00788 case LUN_ID_6:
00789 status = Lun_6_mem_2_ram(*addr , ram);
00790 if (CTRL_GOOD == status)
00791 {
00792 status = Lun_6_mem_2_ram_read();
00793 }
00794 break;
00795 # endif
00796 # if (LUN_7 == ENABLE)
00797 case LUN_ID_7:
00798 status = Lun_7_mem_2_ram(*addr , ram);
00799 if (CTRL_GOOD == status)
00800 {
00801 status = Lun_7_mem_2_ram_read();
00802 }
00803 break;
00804 # endif
00805 # if (LUN_USB == ENABLE)
00806 default:
00807 return Lun_usb_mem_2_ram(*addr , ram);
00808 # endif
00809 }
00810 return status;
00811 }
00812 #endif // ACCESS_MEM_TO_RAM == ENABLED
00813
00814
00815
00816 #if (ACCESS_MEM_TO_RAM==ENABLE)
00817
00818
00819
00820
00821
00822
00823
00824
00825
00826 Ctrl_status ram_2_memory( U8 lun , const U32 _MEM_TYPE_SLOW_ *addr , U8 _MEM_TYPE_SLOW_ * ram )
00827 {
00828 Ctrl_status status;
00829
00830 switch( lun )
00831 {
00832 # if (LUN_0 == ENABLE)
00833 case LUN_ID_0:
00834 status = Lun_0_ram_2_mem(*addr , ram);
00835 if (CTRL_GOOD == status)
00836 {
00837 status = Lun_0_ram_2_mem_write();
00838 }
00839 break;
00840 # endif
00841 # if (LUN_1 == ENABLE)
00842 case LUN_ID_1:
00843 status = Lun_1_ram_2_mem(*addr , ram);
00844 if (CTRL_GOOD == status)
00845 {
00846 status = Lun_1_ram_2_mem_write();
00847 }
00848 break;
00849 # endif
00850 # if (LUN_2 == ENABLE)
00851 case LUN_ID_2:
00852 status = Lun_2_ram_2_mem(*addr , ram);
00853 if (CTRL_GOOD == status)
00854 {
00855 status = Lun_2_ram_2_mem_write();
00856 }
00857 break;
00858 # endif
00859 # if (LUN_3 == ENABLE)
00860 case LUN_ID_3:
00861 status = Lun_3_ram_2_mem(*addr , ram);
00862 if (CTRL_GOOD == status)
00863 {
00864 status = Lun_3_ram_2_mem_write();
00865 }
00866 break;
00867 # endif
00868 # if (LUN_4 == ENABLE)
00869 case LUN_ID_4:
00870 status = Lun_4_ram_2_mem(*addr , ram);
00871 if (CTRL_GOOD == status)
00872 {
00873 status = Lun_4_ram_2_mem_write();
00874 }
00875 break;
00876 # endif
00877 # if (LUN_5 == ENABLE)
00878 case LUN_ID_5:
00879 status = Lun_5_ram_2_mem(*addr , ram);
00880 if (CTRL_GOOD == status)
00881 {
00882 status = Lun_5_ram_2_mem_write();
00883 }
00884 break;
00885 # endif
00886 # if (LUN_6 == ENABLE)
00887 case LUN_ID_6:
00888 status = Lun_6_ram_2_mem(*addr , ram);
00889 if (CTRL_GOOD == status)
00890 {
00891 status = Lun_6_ram_2_mem_write();
00892 }
00893 break;
00894 # endif
00895 # if (LUN_7 == ENABLE)
00896 case LUN_ID_7:
00897 status = Lun_7_ram_2_mem(*addr , ram);
00898 if (CTRL_GOOD == status)
00899 {
00900 status = Lun_7_ram_2_mem_write();
00901 }
00902 break;
00903 # endif
00904 # if (LUN_USB == ENABLE)
00905 default:
00906 return Lun_usb_ram_2_mem(*addr , ram);
00907 break;
00908 # endif
00909 }
00910 return status;
00911 }
00912 #endif // ACCESS_RAM_TO_MEM == ENABLED
00913
00914
00915
00916
00917 #if (ACCESS_STREAM == ENABLED)
00918
00919
00920
00921
00922 # if (ACCESS_MEM_TO_MEM == ENABLED)
00923
00924
00925
00926
00927
00928
00929
00930
00931 U8 stream_mem_to_mem( U8 src_lun , U32 src_addr , U8 dest_lun , U32 dest_addr , U16 nb_sector )
00932 {
00933 while(nb_sector)
00934 {
00935 memory_2_ram( src_lun , &src_addr , buf_sector );
00936 ram_2_memory( dest_lun , &dest_addr , buf_sector );
00937 src_addr++;
00938 dest_addr++;
00939 nb_sector--;
00940 }
00941 return CTRL_GOOD;
00942 }
00943 # endif // ACCESS_MEM_TO_MEM == ENABLED
00944
00945
00946
00947
00948
00949
00950
00951
00952
00953
00954
00955
00956
00957 Ctrl_status stream_state( U8 Id )
00958 {
00959
00960 return CTRL_GOOD;
00961 }
00962
00963
00964
00965
00966
00967
00968
00969 U16 stream_stop( U8 Id )
00970 {
00971 return 0;
00972 }
00973
00974 #endif // ACCESS_STREAM == ENABLED
00975
00976