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00043 #ifndef _USB_DRV_H_
00044 #define _USB_DRV_H_
00045
00046 #include "compiler.h"
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056 typedef enum endpoint_parameter{ep_num, ep_type, ep_direction, ep_size, ep_bank, nyet_status} t_endpoint_parameter;
00057
00058
00059
00060
00061 #define MAX_EP_NB 7
00062
00063 #define EP_CONTROL 0
00064 #define EP_1 1
00065 #define EP_2 2
00066 #define EP_3 3
00067 #define EP_4 4
00068 #define EP_5 5
00069 #define EP_6 6
00070 #define EP_7 7
00071
00072 #define PIPE_CONTROL 0
00073 #define PIPE_0 0
00074 #define PIPE_1 1
00075 #define PIPE_2 2
00076 #define PIPE_3 3
00077 #define PIPE_4 4
00078 #define PIPE_5 5
00079 #define PIPE_6 6
00080 #define PIPE_7 7
00081
00082
00083 #define MSK_EP_DIR 0x7F
00084 #define MSK_UADD 0x7F
00085 #define MSK_EPTYPE 0xC0
00086 #define MSK_EPSIZE 0x70
00087 #define MSK_EPBK 0x0C
00088 #define MSK_DTSEQ 0x0C
00089 #define MSK_NBUSYBK 0x03
00090 #define MSK_CURRBK 0x03
00091 #define MSK_DAT 0xFF // UEDATX
00092 #define MSK_BYCTH 0x07 // UEBCHX
00093 #define MSK_BYCTL 0xFF // UEBCLX
00094 #define MSK_EPINT 0x7F // UEINT
00095 #define MSK_HADDR 0xFF // UHADDR
00096
00097
00098 #define MSK_PNUM 0x07 // UPNUM
00099 #define MSK_PRST 0x7F // UPRST
00100 #define MSK_PTYPE 0xC0 // UPCFG0X
00101 #define MSK_PTOKEN 0x30
00102 #define MSK_PEPNUM 0x0F
00103 #define MSK_PSIZE 0x70 // UPCFG1X
00104 #define MSK_PBK 0x0C
00105
00106 #define MSK_NBUSYBK 0x03
00107
00108 #define MSK_ERROR 0x1F
00109
00110 #define MSK_PTYPE 0xC0 // UPCFG0X
00111 #define MSK_PTOKEN 0x30
00112 #define MSK_TOKEN_SETUP 0x30
00113 #define MSK_TOKEN_IN 0x10
00114 #define MSK_TOKEN_OUT 0x20
00115 #define MSK_PEPNUM 0x0F
00116
00117 #define MSK_PSIZE 0x70 // UPCFG1X
00118 #define MSK_PBK 0x0C
00119
00120
00121
00122
00123 #define TYPE_CONTROL 0
00124 #define TYPE_ISOCHRONOUS 1
00125 #define TYPE_BULK 2
00126 #define TYPE_INTERRUPT 3
00127
00128
00129 #define DIRECTION_OUT 0
00130 #define DIRECTION_IN 1
00131
00132
00133 #define SIZE_8 0
00134 #define SIZE_16 1
00135 #define SIZE_32 2
00136 #define SIZE_64 3
00137 #define SIZE_128 4
00138 #define SIZE_256 5
00139 #define SIZE_512 6
00140 #define SIZE_1024 7
00141
00142
00143
00144 #define ONE_BANK 0
00145 #define TWO_BANKS 1
00146
00147
00148 #define NYET_ENABLED 0
00149 #define NYET_DISABLED 1
00150
00151
00152 #define TOKEN_SETUP 0
00153 #define TOKEN_IN 1
00154 #define TOKEN_OUT 2
00155
00156 #define Is_ep_addr_in(x) ( (x&0x80)? TRUE : FALSE)
00157
00158
00159
00160
00161
00162
00163 #define Usb_build_ep_config0(type, dir, nyet) ((type<<6) | (dir))
00164 #define Usb_build_ep_config1(size, bank ) ((size<<4) | (bank<<2) )
00165 #define usb_configure_endpoint(num, type, dir, size, bank, nyet) \
00166 ( Usb_select_endpoint(num), \
00167 usb_config_ep(Usb_build_ep_config0(type, dir, nyet),\
00168 Usb_build_ep_config1(size, bank) ))
00169
00170 #define Host_build_pipe_config0(type, token, ep_num) ((type<<6) | (token<<4) | (ep_num))
00171 #define Host_build_pipe_config1(size, bank ) ((size<<4) | (bank<<2) )
00172 #define host_configure_pipe(num, type, token,ep_num, size, bank, freq) \
00173 ( Host_select_pipe(num), \
00174 Host_set_interrupt_frequency(freq), \
00175 host_config_pipe(Host_build_pipe_config0(type, token, ep_num),\
00176 Host_build_pipe_config1(size, bank) ))
00177
00178
00179
00180
00181
00182
00183
00184 #define Usb_enable_regulator() (UHWCON |= (1<<UVREGE))
00185
00186 #define Usb_disable_regulator() (UHWCON &= ~(1<<UVREGE))
00187
00188 #define Is_usb_regulator_enabled() ((UHWCON & (1<<UVREGE)) ? TRUE : FALSE)
00189
00190
00191
00192
00193
00194
00195
00196 #define Usb_enable_uid_pin() (UHWCON |= (1<<UIDE))
00197
00198 #define Usb_disable_uid_pin() (UHWCON &= ~(1<<UIDE))
00199
00200 #define Usb_force_device_mode() (Usb_disable_uid_pin(), UHWCON |= (1<<UIMOD))
00201
00202 #define Usb_force_host_mode() (Usb_disable_uid_pin(), UHWCON &= ~(1<<UIMOD))
00203
00204 #define Usb_enable_uvcon_pin() (UHWCON |= (1<<UVCONE))
00205
00206 #define Usb_disable_uvcon_pin() (UHWCON &= ~(1<<UVCONE))
00207
00208 #define Usb_full_speed_mode() (UDCON &= ~(1<<LSM))
00209
00210 #define Usb_low_speed_mode() (UDCON |= (1<<LSM))
00211
00212
00213 #define Usb_enable() (USBCON |= ((1<<USBE) | (1<<OTGPADE)))
00214
00215 #define Usb_disable() (USBCON &= ~((1<<USBE) | (1<<OTGPADE)))
00216 #define Is_usb_enabled() ((USBCON & (1<<USBE)) ? TRUE : FALSE)
00217
00218
00219 #define Usb_enable_vbus_pad() (USBCON |= (1<<OTGPADE))
00220
00221 #define Usb_disable_vbus_pad() (USBCON &= ~(1<<OTGPADE))
00222
00223 #define Usb_select_device() (USBCON &= ~(1<<HOST))
00224 #define Usb_select_host() (USBCON |= (1<<HOST))
00225 #define Is_usb_host_enabled() ((USBCON & (1<<HOST)) ? TRUE : FALSE)
00226
00227
00228 #define Usb_freeze_clock() (USBCON |= (1<<FRZCLK))
00229 #define Usb_unfreeze_clock() (USBCON &= ~(1<<FRZCLK))
00230 #define Is_usb_clock_freezed() ((USBCON & (1<<FRZCLK)) ? TRUE : FALSE)
00231
00232 #define Usb_enable_id_interrupt() (USBCON |= (1<<IDTE))
00233 #define Usb_disable_id_interrupt() (USBCON &= ~(1<<IDTE))
00234 #define Is_usb_id_interrupt_enabled() ((USBCON & (1<<IDTE)) ? TRUE : FALSE)
00235 #define Is_usb_id_device() ((USBSTA & (1<<ID)) ? TRUE : FALSE)
00236 #define Usb_ack_id_transition() (USBINT = ~(1<<IDTI))
00237 #define Is_usb_id_transition() ((USBINT & (1<<IDTI)) ? TRUE : FALSE)
00238
00239 #define Usb_enable_vbus_interrupt() (USBCON |= (1<<VBUSTE))
00240 #define Usb_disable_vbus_interrupt() (USBCON &= ~(1<<VBUSTE))
00241 #define Is_usb_vbus_interrupt_enabled() ((USBCON & (1<<VBUSTE)) ? TRUE : FALSE)
00242 #define Is_usb_vbus_high() ((USBSTA & (1<<VBUS)) ? TRUE : FALSE)
00243 #define Is_usb_vbus_low() ((USBSTA & (1<<VBUS)) ? FALSE : TRUE)
00244 #define Usb_ack_vbus_transition() (USBINT = ~(1<<VBUSTI))
00245 #define Is_usb_vbus_transition() ((USBINT & (1<<VBUSTI)) ? TRUE : FALSE)
00246
00247
00248 #define Usb_get_general_interrupt() (USBINT & (USBCON & MSK_IDTE_VBUSTE))
00249
00250 #define Usb_ack_all_general_interrupt() (USBINT = ~(USBCON & MSK_IDTE_VBUSTE))
00251 #define Usb_ack_cache_id_transition(x) ((x) &= ~(1<<IDTI))
00252 #define Usb_ack_cache_vbus_transition(x) ((x) &= ~(1<<VBUSTI))
00253 #define Is_usb_cache_id_transition(x) (((x) & (1<<IDTI)) )
00254 #define Is_usb_cache_vbus_transition(x) (((x) & (1<<VBUSTI)))
00255
00256
00257 #define Usb_get_otg_interrupt() (OTGINT & OTGIEN)
00258
00259 #define Usb_ack_all_otg_interrupt() (OTGINT = ~OTGIEN)
00260 #define Is_otg_cache_bconnection_error(x) (((x) & MSK_BCERRI))
00261 #define Usb_ack_cache_bconnection_error(x) ((x) &= ~MSK_BCERRI)
00262
00263 #define Usb_enter_dpram_mode() (UDPADDH = (1<<DPACC))
00264 #define Usb_exit_dpram_mode() (UDPADDH = (U8)~(1<<DPACC))
00265 #define Usb_set_dpram_address(addr) (UDPADDH = (1<<DPACC) + ((Uint16)addr >> 8), UDPADDL = (Uchar)addr)
00266 #define Usb_write_dpram_byte(val) (UEDATX=val)
00267 #define Usb_read_dpram_byte() (UEDATX)
00268
00269
00270 #define Usb_enable_vbus() (OTGCON |= (1<<VBUSREQ))
00271
00272 #define Usb_disable_vbus() (OTGCON |= (1<<VBUSRQC))
00273
00274 #define Usb_enable_manual_vbus() (PORTE|=0x80,DDRE|=0x80,Usb_disable_uvcon_pin())
00275
00276
00277 #define Usb_device_initiate_hnp() (OTGCON |= (1<<HNPREQ))
00278
00279 #define Usb_host_accept_hnp() (OTGCON |= (1<<HNPREQ))
00280
00281 #define Usb_host_reject_hnp() (OTGCON &= ~(1<<HNPREQ))
00282
00283 #define Usb_device_initiate_srp() (OTGCON |= (1<<SRPREQ))
00284
00285 #define Usb_select_vbus_srp_method() (OTGCON |= (1<<SRPSEL))
00286
00287 #define Usb_select_data_srp_method() (OTGCON &= ~(1<<SRPSEL))
00288
00289 #define Usb_enable_vbus_hw_control() (OTGCON &= ~(1<<VBUSHWC))
00290
00291 #define Usb_disable_vbus_hw_control() (OTGCON |= (1<<VBUSHWC))
00292
00293 #define Is_usb_vbus_enabled() ((OTGCON & (1<<VBUSREQ)) ? TRUE : FALSE)
00294
00295 #define Is_usb_hnp() ((OTGCON & (1<<HNPREQ)) ? TRUE : FALSE)
00296
00297 #define Is_usb_device_srp() ((OTGCON & (1<<SRPREQ)) ? TRUE : FALSE)
00298
00299
00300 #define Usb_enable_suspend_time_out_interrupt() (OTGIEN |= (1<<STOE))
00301
00302 #define Usb_disable_suspend_time_out_interrupt() (OTGIEN &= ~(1<<STOE))
00303 #define Is_suspend_time_out_interrupt_enabled() ((OTGIEN & (1<<STOE)) ? TRUE : FALSE)
00304
00305 #define Usb_ack_suspend_time_out_interrupt() (OTGINT &= ~(1<<STOI))
00306
00307 #define Is_usb_suspend_time_out_interrupt() ((OTGINT & (1<<STOI)) ? TRUE : FALSE)
00308
00309
00310 #define Usb_enable_hnp_error_interrupt() (OTGIEN |= (1<<HNPERRE))
00311
00312 #define Usb_disable_hnp_error_interrupt() (OTGIEN &= ~(1<<HNPERRE))
00313 #define Is_hnp_error_interrupt_enabled() ((OTGIEN & (1<<HNPERRE)) ? TRUE : FALSE)
00314
00315 #define Usb_ack_hnp_error_interrupt() (OTGINT &= ~(1<<HNPERRI))
00316
00317 #define Is_usb_hnp_error_interrupt() ((OTGINT & (1<<HNPERRI)) ? TRUE : FALSE)
00318
00319
00320 #define Usb_enable_role_exchange_interrupt() (OTGIEN |= (1<<ROLEEXE))
00321
00322 #define Usb_disable_role_exchange_interrupt() (OTGIEN &= ~(1<<ROLEEXE))
00323 #define Is_role_exchange_interrupt_enabled() ((OTGIEN & (1<<ROLEEXE)) ? TRUE : FALSE)
00324
00325 #define Usb_ack_role_exchange_interrupt() (OTGINT &= ~(1<<ROLEEXI))
00326
00327 #define Is_usb_role_exchange_interrupt() ((OTGINT & (1<<ROLEEXI)) ? TRUE : FALSE)
00328
00329
00330 #define Usb_enable_bconnection_error_interrupt() (OTGIEN |= (1<<BCERRE))
00331
00332 #define Usb_disable_bconnection_error_interrupt() (OTGIEN &= ~(1<<BCERRE))
00333 #define Is_bconnection_error_interrupt_enabled() ((OTGIEN & (1<<BCERRE)) ? TRUE : FALSE)
00334
00335 #define Usb_ack_bconnection_error_interrupt() (OTGINT &= ~(1<<BCERRI))
00336
00337 #define Is_usb_bconnection_error_interrupt() ((OTGINT & (1<<BCERRI)) ? TRUE : FALSE)
00338
00339
00340 #define Usb_enable_vbus_error_interrupt() (OTGIEN |= (1<<VBERRE))
00341
00342 #define Usb_disable_vbus_error_interrupt() (OTGIEN &= ~(1<<VBERRE))
00343 #define Is_vbus_error_interrupt_enabled() ((OTGIEN & (1<<VBERRE)) ? TRUE : FALSE)
00344
00345 #define Usb_ack_vbus_error_interrupt() (OTGINT &= ~(1<<VBERRI))
00346
00347 #define Is_usb_vbus_error_interrupt() ((OTGINT & (1<<VBERRI)) ? TRUE : FALSE)
00348
00349
00350 #define Usb_enable_srp_interrupt() (OTGIEN |= (1<<SRPE))
00351
00352 #define Usb_disable_srp_interrupt() (OTGIEN &= ~(1<<SRPE))
00353 #define Is_srp_interrupt_enabled() ((OTGIEN & (1<<SRPE)) ? TRUE : FALSE)
00354
00355 #define Usb_ack_srp_interrupt() (OTGINT &= ~(1<<SRPI))
00356
00357 #define Is_usb_srp_interrupt() ((OTGINT & (1<<SRPI)) ? TRUE : FALSE)
00358
00359
00360
00361
00362
00363
00364
00365 #define Usb_initiate_remote_wake_up() (UDCON |= (1<<RMWKUP))
00366
00367 #define Usb_detach() (UDCON |= (1<<DETACH))
00368
00369 #define Usb_attach() (UDCON &= ~(1<<DETACH))
00370
00371 #define Is_usb_pending_remote_wake_up() ((UDCON & (1<<RMWKUP)) ? TRUE : FALSE)
00372
00373 #define Is_usb_detached() ((UDCON & (1<<DETACH)) ? TRUE : FALSE)
00374
00375
00376 #define Usb_get_device_interrupt() (UDINT & (1<<UDIEN))
00377
00378 #define Usb_ack_all_device_interrupt() (UDINT = ~(1<<UDIEN))
00379
00380
00381 #define Usb_enable_remote_wake_up_interrupt() (UDIEN |= (1<<UPRSME))
00382
00383 #define Usb_disable_remote_wake_up_interrupt() (UDIEN &= ~(1<<UPRSME))
00384 #define Is_remote_wake_up_interrupt_enabled() ((UDIEN & (1<<UPRSME)) ? TRUE : FALSE)
00385
00386 #define Usb_ack_remote_wake_up_start() (UDINT = ~(1<<UPRSMI))
00387
00388 #define Is_usb_remote_wake_up_start() ((UDINT & (1<<UPRSMI)) ? TRUE : FALSE)
00389
00390
00391 #define Usb_enable_resume_interrupt() (UDIEN |= (1<<EORSME))
00392
00393 #define Usb_disable_resume_interrupt() (UDIEN &= ~(1<<EORSME))
00394 #define Is_resume_interrupt_enabled() ((UDIEN & (1<<EORSME)) ? TRUE : FALSE)
00395
00396 #define Usb_ack_resume() (UDINT = ~(1<<EORSMI))
00397
00398 #define Is_usb_resume() ((UDINT & (1<<EORSMI)) ? TRUE : FALSE)
00399
00400
00401 #define Usb_enable_wake_up_interrupt() (UDIEN |= (1<<WAKEUPE))
00402
00403 #define Usb_disable_wake_up_interrupt() (UDIEN &= ~(1<<WAKEUPE))
00404 #define Is_swake_up_interrupt_enabled() ((UDIEN & (1<<WAKEUPE)) ? TRUE : FALSE)
00405
00406 #define Usb_ack_wake_up() (UDINT = ~(1<<WAKEUPI))
00407
00408 #define Is_usb_wake_up() ((UDINT & (1<<WAKEUPI)) ? TRUE : FALSE)
00409
00410
00411 #define Usb_enable_reset_interrupt() (UDIEN |= (1<<EORSTE))
00412
00413 #define Usb_disable_reset_interrupt() (UDIEN &= ~(1<<EORSTE))
00414 #define Is_reset_interrupt_enabled() ((UDIEN & (1<<EORSTE)) ? TRUE : FALSE)
00415
00416 #define Usb_ack_reset() (UDINT = ~(1<<EORSTI))
00417
00418 #define Is_usb_reset() ((UDINT & (1<<EORSTI)) ? TRUE : FALSE)
00419
00420
00421 #define Usb_enable_sof_interrupt() (UDIEN |= (1<<SOFE))
00422
00423 #define Usb_disable_sof_interrupt() (UDIEN &= ~(1<<SOFE))
00424 #define Is_sof_interrupt_enabled() ((UDIEN & (1<<SOFE)) ? TRUE : FALSE)
00425
00426 #define Usb_ack_sof() (UDINT = ~(1<<SOFI))
00427
00428 #define Is_usb_sof() ((UDINT & (1<<SOFI)) ? TRUE : FALSE)
00429
00430
00431 #define Usb_enable_suspend_interrupt() (UDIEN |= (1<<SUSPE))
00432
00433 #define Usb_disable_suspend_interrupt() (UDIEN &= ~(1<<SUSPE))
00434 #define Is_suspend_interrupt_enabled() ((UDIEN & (1<<SUSPE)) ? TRUE : FALSE)
00435
00436 #define Usb_ack_suspend() (UDINT = ~(1<<SUSPI))
00437
00438 #define Is_usb_suspend() ((UDINT & (1<<SUSPI)) ? TRUE : FALSE)
00439
00440
00441 #define Usb_enable_address() (UDADDR |= (1<<ADDEN))
00442
00443 #define Usb_disable_address() (UDADDR &= ~(1<<ADDEN))
00444
00445 #define Usb_configure_address(addr) (UDADDR = (UDADDR & (1<<ADDEN)) | ((U8)addr & MSK_UADD))
00446
00447
00448 #define Usb_frame_number() ((U16)((((U16)UDFNUMH) << 8) | ((U16)UDFNUML)))
00449
00450 #define Is_usb_frame_number_crc_error() ((UDMFN & (1<<FNCERR)) ? TRUE : FALSE)
00451
00452
00453
00454
00455
00456
00457
00458
00459
00460 #define Usb_select_endpoint(ep) (UENUM = (U8)ep )
00461
00462
00463 #define Usb_get_selected_endpoint() (UENUM )
00464
00465
00466 #define Usb_reset_endpoint(ep) (UERST = 1 << (U8)ep, UERST = 0)
00467
00468
00469 #define Usb_enable_endpoint() (UECONX |= (1<<EPEN))
00470
00471 #define Usb_enable_stall_handshake() (UECONX |= (1<<STALLRQ))
00472
00473 #define Usb_reset_data_toggle() (UECONX |= (1<<RSTDT))
00474
00475 #define Usb_disable_endpoint() (UECONX &= ~(1<<EPEN))
00476
00477 #define Usb_disable_stall_handshake() (UECONX |= (1<<STALLRQC))
00478
00479 #define Usb_select_epnum_for_cpu() (UECONX &= ~(1<<EPNUMS))
00480
00481 #define Is_usb_endpoint_enabled() ((UECONX & (1<<EPEN)) ? TRUE : FALSE)
00482
00483 #define Is_usb_endpoint_stall_requested() ((UECONX & (1<<STALLRQ)) ? TRUE : FALSE)
00484
00485
00486 #define Usb_configure_endpoint_type(type) (UECFG0X = (UECFG0X & ~(MSK_EPTYPE)) | ((U8)type << 6))
00487
00488 #define Usb_configure_endpoint_direction(dir) (UECFG0X = (UECFG0X & ~(1<<EPDIR)) | ((U8)dir))
00489
00490
00491 #define Usb_configure_endpoint_size(size) (UECFG1X = (UECFG1X & ~MSK_EPSIZE) | ((U8)size << 4))
00492
00493 #define Usb_configure_endpoint_bank(bank) (UECFG1X = (UECFG1X & ~MSK_EPBK) | ((U8)bank << 2))
00494
00495 #define Usb_allocate_memory() (UECFG1X |= (1<<ALLOC))
00496
00497 #define Usb_unallocate_memory() (UECFG1X &= ~(1<<ALLOC))
00498
00499
00500 #define Usb_ack_overflow_interrupt() (UESTA0X &= ~(1<<OVERFI))
00501
00502 #define Usb_ack_underflow_interrupt() (UESTA0X &= ~(1<<UNDERFI))
00503
00504 #define Usb_ack_zlp() (UESTA0X &= ~(1<<ZLPSEEN))
00505
00506 #define Usb_data_toggle() ((UESTA0X&MSK_DTSEQ) >> 2)
00507
00508 #define Usb_nb_busy_bank() (UESTA0X & MSK_NBUSYBK)
00509
00510 #define Is_usb_one_bank_busy() ((UESTA0X & MSK_NBUSYBK) == 0 ? FALSE : TRUE)
00511
00512 #define Is_endpoint_configured() ((UESTA0X & (1<<CFGOK)) ? TRUE : FALSE)
00513
00514 #define Is_usb_overflow() ((UESTA0X & (1<<OVERFI)) ? TRUE : FALSE)
00515
00516 #define Is_usb_underflow() ((UESTA0X & (1<<UNDERFI)) ? TRUE : FALSE)
00517
00518 #define Is_usb_zlp() ((UESTA0X & (1<<ZLPSEEN)) ? TRUE : FALSE)
00519
00520
00521 #define Usb_control_direction() ((UESTA1X & (1<<CTRLDIR)) >> 2)
00522
00523 #define Usb_current_bank() ( UESTA1X & MSK_CURRBK)
00524
00525
00526 #define Usb_ack_fifocon() (UEINTX &= ~(1<<FIFOCON))
00527
00528 #define Usb_ack_nak_in() (UEINTX &= ~(1<<NAKINI))
00529
00530 #define Usb_ack_nak_out() (UEINTX &= ~(1<<NAKOUTI))
00531
00532 #define Usb_ack_receive_setup() (UEINTX &= ~(1<<RXSTPI))
00533
00534 #define Is_usb_receive_nak_in() (UEINTX &(1<<NAKINI))
00535
00536 #define Is_usb_receive_nak_out() (UEINTX &(1<<NAKOUTI))
00537
00538 #define Usb_ack_receive_out() (UEINTX &= ~(1<<RXOUTI), Usb_ack_fifocon())
00539
00540 #define Usb_ack_stalled() (MSK_STALLEDI= 0)
00541
00542 #define Usb_ack_in_ready() (UEINTX &= ~(1<<TXINI), Usb_ack_fifocon())
00543
00544 #define Usb_kill_last_in_bank() (UENTTX |= (1<<RXOUTI))
00545
00546 #define Is_usb_read_enabled() (UEINTX&(1<<RWAL))
00547
00548 #define Is_usb_write_enabled() (UEINTX&(1<<RWAL))
00549
00550 #define Is_usb_read_control_enabled() (UEINTX&(1<<TXINI))
00551
00552 #define Is_usb_receive_setup() (UEINTX&(1<<RXSTPI))
00553
00554 #define Is_usb_receive_out() (UEINTX&(1<<RXOUTI))
00555
00556 #define Is_usb_in_ready() (UEINTX&(1<<TXINI))
00557
00558 #define Usb_send_in() (UEINTX &= ~(1<<FIFOCON))
00559
00560 #define Usb_send_control_in() (UEINTX &= ~(1<<TXINI))
00561
00562 #define Usb_free_out_bank() (UEINTX &= ~(1<<FIFOCON))
00563
00564 #define Usb_ack_control_out() (UEINTX &= ~(1<<RXOUTI))
00565
00566
00567 #define Usb_enable_flow_error_interrupt() (UEIENX |= (1<<FLERRE))
00568
00569 #define Usb_enable_nak_in_interrupt() (UEIENX |= (1<<NAKINE))
00570
00571 #define Usb_enable_nak_out_interrupt() (UEIENX |= (1<<NAKOUTE))
00572
00573 #define Usb_enable_receive_setup_interrupt() (UEIENX |= (1<<RXSTPE))
00574
00575 #define Usb_enable_receive_out_interrupt() (UEIENX |= (1<<RXOUTE))
00576
00577 #define Usb_enable_stalled_interrupt() (UEIENX |= (1<<STALLEDE))
00578
00579 #define Usb_enable_in_ready_interrupt() (UEIENX |= (1<<TXINE))
00580
00581 #define Usb_disable_flow_error_interrupt() (UEIENX &= ~(1<<FLERRE))
00582
00583 #define Usb_disable_nak_in_interrupt() (UEIENX &= ~(1<<NAKINE))
00584
00585 #define Usb_disable_nak_out_interrupt() (UEIENX &= ~(1<<NAKOUTE))
00586
00587 #define Usb_disable_receive_setup_interrupt() (UEIENX &= ~(1<<RXSTPE))
00588
00589 #define Usb_disable_receive_out_interrupt() (UEIENX &= ~(1<<RXOUTE))
00590
00591 #define Usb_disable_stalled_interrupt() (UEIENX &= ~(1<<STALLEDE))
00592
00593 #define Usb_disable_in_ready_interrupt() (UEIENX &= ~(1<<TXIN))
00594
00595
00596 #define Usb_read_byte() (UEDATX)
00597
00598 #define Usb_write_byte(byte) (UEDATX = (U8)byte)
00599
00600
00601 #define Usb_byte_counter() ((((U16)UEBCHX) << 8) | (UEBCLX))
00602
00603 #define Usb_byte_counter_8() ((U8)UEBCLX)
00604
00605
00606 #define Usb_interrupt_flags() (UEINT)
00607
00608 #define Is_usb_endpoint_event() (Usb_interrupt_flags() != 0x00)
00609
00610
00611
00612
00613
00614
00615
00616
00617 #define Host_allocate_memory() (UPCFG1X |= (1<<ALLOC))
00618
00619 #define Host_unallocate_memory() (UPCFG1X &= ~(1<<ALLOC))
00620
00621
00622 #define Host_enable() (USBCON |= (1<<HOST))
00623
00624 #ifndef SOFEN
00625 #define SOFEN 0 //For AVRGCC, SOFEN bit missing in default sfr file
00626 #endif
00627
00628 #define Host_enable_sof() (UHCON |= (1<<SOFEN))
00629
00630 #define Host_disable_sof() (UHCON &= ~(1<<SOFEN))
00631
00632 #define Host_send_reset() (UHCON |= (1<<RESET))
00633
00634 #define Host_is_reset() ((UHCON & (1<<RESET)) ? TRUE : FALSE)
00635
00636 #define Host_send_resume() (UHCON |= (1<<RESUME))
00637
00638 #define Host_is_resume() ((UHCON & (1<<RESUME)) ? TRUE : FALSE)
00639
00640
00641 #define Host_enable_sof_interrupt() (UHIEN |= (1<<HSOFE))
00642
00643 #define Host_disable_sof_interrupt() (UHIEN &= ~(1<<HSOFE))
00644 #define Is_host_sof_interrupt_enabled() ((UHIEN & (1<<HSOFE)) ? TRUE : FALSE)
00645
00646 #define Host_is_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
00647 #define Is_host_sof() ((UHINT & (1<<HSOFI)) ? TRUE : FALSE)
00648 #define Host_ack_sof() (UHINT &= ~(1<<HSOFI))
00649
00650
00651 #define Host_enable_hwup_interrupt() (UHIEN |= (1<<HWUPE))
00652
00653 #define Host_disable_hwup_interrupt() (UHIEN &= ~(1<<HWUPE))
00654 #define Is_host_hwup_interrupt_enabled() ((UHIEN & (1<<HWUPE)) ? TRUE : FALSE)
00655
00656 #define Host_is_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
00657
00658 #define Is_host_hwup() ((UHINT & (1<<HWUPI)) ? TRUE : FALSE)
00659 #define Host_ack_hwup() (UHINT &= ~(1<<HWUPI))
00660
00661
00662 #define Host_enable_down_stream_resume_interrupt() (UHIEN |= (1<<RSMEDE))
00663
00664 #define Host_disable_down_stream_resume_interrupt() (UHIEN &= ~(1<<RSMEDE))
00665 #define Is_host_down_stream_resume_interrupt_enabled() ((UHIEN & (1<<RSMEDE)) ? TRUE : FALSE)
00666
00667 #define Is_host_down_stream_resume() ((UHINT & (1<<RSMEDI)) ? TRUE : FALSE)
00668 #define Host_ack_down_stream_resume() (UHINT &= ~(1<<RSMEDI))
00669
00670
00671 #define Host_enable_remote_wakeup_interrupt() (UHIEN |= (1<<RXRSME))
00672
00673 #define Host_disable_remote_wakeup_interrupt() (UHIEN &= ~(1<<RXRSME))
00674 #define Is_host_remote_wakeup_interrupt_enabled() ((UHIEN & (1<<RXRSME)) ? TRUE : FALSE)
00675
00676 #define Host_is_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
00677
00678 #define Is_host_remote_wakeup() ((UHINT & (1<<RXRSMI)) ? TRUE : FALSE)
00679 #define Host_ack_remote_wakeup() (UHINT &= ~(1<<RXRSMI))
00680
00681
00682 #define Host_enable_device_connection_interrupt() (UHIEN |= (1<<DCONNE))
00683
00684 #define Host_disable_device_connection_interrupt() (UHIEN &= ~(1<<DCONNE))
00685 #define Is_host_device_connection_interrupt_enabled() ((UHIEN & (1<<DCONNE)) ? TRUE : FALSE)
00686
00687 #define Is_device_connection() (UHINT & (1<<DCONNI))
00688
00689 #define Host_ack_device_connection() (UHINT = ~(1<<DCONNI))
00690
00691
00692 #define Host_enable_device_disconnection_interrupt() (UHIEN |= (1<<DDISCE))
00693
00694 #define Host_disable_device_disconnection_interrupt() (UHIEN &= ~(1<<DDISCE))
00695 #define Is_host_device_disconnection_interrupt_enabled() ((UHIEN & (1<<DDISCE)) ? TRUE : FALSE)
00696
00697 #define Is_device_disconnection() (UHINT & (1<<DDISCI) ? TRUE : FALSE)
00698
00699 #define Host_ack_device_disconnection() (UHINT = ~(1<<DDISCI))
00700
00701
00702 #define Host_enable_reset_interrupt() (UHIEN |= (1<<RSTE))
00703
00704 #define Host_disable_reset_interrupt() (UHIEN &= ~(1<<RSTE))
00705 #define Is_host_reset_interrupt_enabled() ((UHIEN & (1<<RSTE)) ? TRUE : FALSE)
00706
00707 #define Host_ack_reset() (UHINT = ~(1<<RSTI))
00708
00709 #define Is_host_reset() Host_is_reset()
00710
00711
00712
00713 #define Host_vbus_request() (OTGCON |= (1<<VBUSREQ))
00714
00715 #define Host_clear_vbus_request() (OTGCON |= (1<<VBUSRQC))
00716
00717 #define Host_configure_address(addr) (UHADDR = addr & MSK_HADDR)
00718
00719
00720 #define Is_host_full_speed() ((USBSTA & (1<<SPEED)) ? TRUE : FALSE)
00721
00722
00723
00724
00725
00726
00727
00728
00729 #define Host_select_pipe(p) (UPNUM = (U8)p)
00730
00731
00732 #define Host_get_selected_pipe() (UPNUM )
00733
00734
00735 #define Host_enable_pipe() (UPCONX |= (1<<PEN))
00736
00737 #define Host_disable_pipe() (UPCONX &= ~(1<<PEN))
00738
00739
00740 #define Host_set_token_setup() (UPCFG0X = UPCFG0X & ~MSK_TOKEN_SETUP)
00741
00742 #define Host_set_token_in() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_IN)
00743
00744 #define Host_set_token_out() (UPCFG0X = (UPCFG0X & ~MSK_TOKEN_SETUP) | MSK_TOKEN_OUT)
00745
00746
00747 #define Host_get_endpoint_number() (UPCFG0X & (MSK_PEPNUM))
00748
00749
00750 #define Host_get_pipe_interrupt() (UPINT)
00751
00752
00753 #define Host_set_interrupt_frequency(frq) (UPCFG2X = (U8)frq)
00754
00755
00756 #define Is_pipe_configured() (UPSTAX & (1<<CFGOK))
00757
00758 #define Is_host_one_bank_busy() ((UPSTAX & (1<<MSK_NBUSYBK)) != 0)
00759
00760 #define Host_number_of_busy_bank() (UPSTAX & (1<<MSK_NBUSYBK))
00761
00762
00763 #define Host_reset_pipe(p) (UPRST = 1<<p , UPRST = 0)
00764
00765
00766 #define Host_write_byte(dat) (UPDATX = dat)
00767
00768 #define Host_read_byte() (UPDATX)
00769
00770
00771 #define Host_freeze_pipe() (UPCONX |= (1<<PFREEZE))
00772
00773 #define Host_unfreeze_pipe() (UPCONX &= ~(1<<PFREEZE))
00774
00775 #define Is_host_pipe_freeze() (UPCONX & (1<<PFREEZE))
00776
00777
00778 #define Host_reset_pipe_data_toggle() (UPCONX |= (1<<RSTDT) )
00779
00780
00781 #define Is_host_setup_sent() ((UPINTX & (1<<TXSTPI)) ? TRUE : FALSE)
00782
00783 #define Is_host_control_in_received() ((UPINTX & (1<<RXINI)) ? TRUE : FALSE)
00784
00785 #define Is_host_control_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
00786
00787 #define Is_host_stall() ((UPINTX & (1<<RXSTALLI)) ? TRUE : FALSE)
00788
00789 #define Is_host_pipe_error() ((UPINTX & (1<<PERRI)) ? TRUE : FALSE)
00790
00791 #define Host_send_setup() (UPINTX &= ~(1<<FIFOCON))
00792
00793 #define Host_send_control_in() (UPINTX &= ~(1<<FIFOCON))
00794
00795 #define Host_send_control_out() (UPINTX &= ~(1<<FIFOCON))
00796
00797 #define Host_ack_control_out() (UPINTX &= ~(1<<TXOUTI))
00798
00799 #define Host_ack_control_in() (UPINTX &= ~(1<<RXINI))
00800
00801 #define Host_ack_setup() (UPINTX &= ~(1<<TXSTPI))
00802
00803 #define Host_ack_stall() (UPINTX &= ~(1<<RXSTALLI))
00804
00805
00806 #define Host_send_out() (UPINTX &= ~(1<<FIFOCON))
00807
00808 #define Is_host_out_sent() ((UPINTX & (1<<TXOUTI)) ? TRUE : FALSE)
00809
00810 #define Host_ack_out_sent() (UPINTX &= ~(1<<TXOUTI))
00811
00812 #define Is_host_in_received() ((UPINTX & (1<<RXINI)) ? TRUE : FALSE)
00813
00814 #define Host_ack_in_received() (UPINTX &= ~(1<<RXINI))
00815
00816 #define Host_send_in() (UPINTX &= ~(1<<FIFOCON))
00817
00818 #define Is_host_nak_received() ((UPINTX & (1<<NAKEDI)) ? TRUE : FALSE)
00819
00820 #define Host_ack_nak_received() (UPINTX &= ~(1<<NAKEDI))
00821
00822
00823
00824
00825 #define Is_host_read_enabled() (UPINTX&(1<<RWAL))
00826
00827 #define Is_host_write_enabled() (UPINTX&(1<<RWAL))
00828
00829
00830 #define Host_standard_in_mode() (UPCONX &= ~(1<<INMODE))
00831
00832 #define Host_continuous_in_mode() (UPCONX |= (1<<INMODE))
00833
00834
00835 #define Host_in_request_number(in_num) (UPINRQX = (U8)in_num)
00836
00837 #define Host_get_in_request_number() (UPINRQX)
00838
00839
00840 #define Host_data_length_U8() (UPBCLX)
00841
00842 #define Host_data_length_U16() ((((U16)UPBCHX)<<8) | UPBCLX)
00843
00844 #define Host_byte_counter() Host_data_length_U16()
00845
00846 #define Host_byte_counter_8() Host_data_length_U8()
00847
00848
00849 #define Host_get_pipe_length() ((U16)0x08 << ((UPCFG1X & MSK_PSIZE)>>4))
00850
00851
00852 #define Host_get_pipe_type() (UPCFG0X>>6)
00853
00854
00855 #define Host_error_status() (UPERRX & MSK_ERROR)
00856
00857 #define Host_ack_all_errors() (UPERRX = 0x00)
00858
00859
00860 #define Host_enable_transmit_interrupt() (UPIENX |= (1<<TXOUTE))
00861
00862 #define Host_disable_transmit_interrupt() (UPIENX &= ~(1<<TXOUTE))
00863
00864
00865 #define Host_enable_receive_interrupt() (UPIENX |= (1<<RXINE))
00866
00867 #define Host_disable_receive_interrupt() (UPIENX &= ~(1<<RXINE))
00868
00869
00870 #define Host_enable_stall_interrupt() (UPIENX |= (1<<RXSTALLE))
00871
00872 #define Host_disable_stall_interrupt() (UPIENX &= ~(1<<RXSTALLE))
00873
00874
00875 #define Host_enable_error_interrupt() (UPIENX |= (1<<PERRE))
00876
00877 #define Host_disable_error_interrupt() (UPIENX &= ~(1<<PERRE))
00878
00879
00880 #define Host_enable_nak_interrupt() (UPIENX |= (1<<NAKEDE))
00881
00882 #define Host_disable_nak_interrupt() (UPIENX &= ~(1<<NAKEDE))
00883
00884 #define Get_pipe_token(x) ((x & (0x80)) ? TOKEN_IN : TOKEN_OUT)
00885
00886
00887
00888
00889
00890
00891
00892
00893
00894
00895 #define wSWAP(x) \
00896 ( (((x)>>8)&0x00FF) \
00897 | (((x)<<8)&0xFF00) \
00898 )
00899
00900
00901
00902
00903
00904
00905
00906
00907
00908 #if !defined(BIG_ENDIAN) && !defined(LITTLE_ENDIAN)
00909 #error YOU MUST Define the Endian Type of target: LITTLE_ENDIAN or BIG_ENDIAN
00910 #endif
00911 #ifdef LITTLE_ENDIAN
00912 #define Usb_write_word_enum_struc(x) (x)
00913 #else //BIG_ENDIAN
00914 #define Usb_write_word_enum_struc(x) (wSWAP(x))
00915 #endif
00916
00917
00918
00919
00920 U8 usb_config_ep (U8, U8);
00921 U8 usb_select_enpoint_interrupt (void);
00922 U8 usb_send_packet (U8 , U8*, U8);
00923 U8 usb_read_packet (U8 , U8*, U8);
00924 void usb_halt_endpoint (U8);
00925 U8 usb_init_device (void);
00926
00927 U8 host_config_pipe (U8, U8);
00928 U8 host_determine_pipe_size (U16);
00929 void host_disable_all_pipe (void);
00930 U8 usb_get_nb_pipe_interrupt (void);
00931
00932 U8 usb_endpoint_wait_for_read_control_enabled();
00933 U8 usb_endpoint_wait_for_write_enabled();
00934 U8 usb_endpoint_wait_for_receive_out();
00935 U8 usb_endpoint_wait_for_IN_ready();
00936
00937 #define usb_endpoint_wait_for_read_enabled usb_endpoint_wait_for_write_enabled
00938
00939 #endif // _USB_DRV_H_
00940
00941