dma.h File Reference

DMA driver header. More...

#include "banked.h"
#include "cc2430_sfr.h"

Go to the source code of this file.

Data Structures
struct	dma_config_t
	DMA configuration structure. More...
Enumerations
enum	dma_trigger_t {   DMA_T_NONE = 0, DMA_T_PREV = 1, DMA_T_T1_CH0 = 2, DMA_T_T1_CH1 = 3,   DMA_T_T1_CH2 = 4, DMA_T_T2_COMP = 5, DMA_T_T2_OVFL = 6, DMA_T_T3_CH0 = 7,   DMA_T_T3_CH1 = 8, DMA_T_T4_CH0 = 9, DMA_T_T4_CH1 = 10, DMA_T_ST = 11,   DMA_T_IOC_0 = 12, DMA_T_IOC_1 = 13, DMA_T_URX0 = 14, DMA_T_UTX0 = 15,   DMA_T_URX1 = 16, DMA_T_UTX1 = 17, DMA_T_FLASH = 18, DMA_T_RADIO = 19,   DMA_T_ADC_CHALL = 20, DMA_T_ADC_CH11 = 21, DMA_T_ADC_CH21 = 22, DMA_T_ADC_CH32 = 23,   DMA_T_ADC_CH42 = 24, DMA_T_ADC_CH53 = 25, DMA_T_ADC_CH63 = 26, DMA_T_ADC_CH74 = 27,   DMA_T_ADC_CH84 = 28, DMA_T_ENC_DW = 29, DMA_T_ENC_UP = 30 }
	DMA triggers. More...
enum	dma_vlen_t {   DMA_VLEN_LEN = (0 << 5), DMA_VLEN_N1 = (1 << 5), DMA_VLEN_N = (2 << 5), DMA_VLEN_N2 = (3 << 5),   DMA_VLEN_N3 = (4 << 5), DMA_VLEN_RES1 = (5 << 5), DMA_VLEN_RES2 = (6 << 5), DMA_VLEN_LEN2 = (7 << 5) }
	variable DMA length modes More...
enum	dma_inc_t { DMA_NOINC = 0, DMA_INC = 1, DMA_INC2 = 2, DMA_DEC = 3 }
	address increment modes More...
enum	dma_type_t { DMA_SINGLE = 0, DMA_BLOCK = 1, DMA_RPT = 2, DMA_BLOCK_RPT = 3 }
	transfer types More...
Functions
void	dma_ISR (void) __interrupt(DMA_VECTOR)
	DMA interrupt service routine.

---

Detailed Description

DMA driver header.

Author:

Original: Martti Huttunen <martti@sensinode.com> Port: Zach Shelby <zach@sensinode.com>

Definition in file dma.h.

---

Enumeration Type Documentation

enum dma_inc_t

address increment modes

Enumerator:

DMA_NOINC	No increment
DMA_INC	Increment
DMA_INC2	Increment 2
DMA_DEC	Decrement

Definition at line 65 of file dma.h.

enum dma_trigger_t

DMA triggers.

Enumerator:

DMA_T_NONE	DMA No trigger, setting DMAREQ.DMAREQx bit starts transfer
DMA_T_PREV	DMA DMA channel is triggered by completion of previous channel
DMA_T_T1_CH0	Timer 1 Timer 1, compare, channel 0
DMA_T_T1_CH1	Timer 1 Timer 1, compare, channel 1
DMA_T_T1_CH2	Timer 1 Timer 1, compare, channel 2
DMA_T_T2_COMP	Timer 2 Timer 2, compare
DMA_T_T2_OVFL	Timer 2 Timer 2, overflow
DMA_T_T3_CH0	Timer 3 Timer 3, compare, channel 0
DMA_T_T3_CH1	Timer 3 Timer 3, compare, channel 1
DMA_T_T4_CH0	Timer 4 Timer 4, compare, channel 0
DMA_T_T4_CH1	Timer 4 Timer 4, compare, channel 1
DMA_T_ST	Sleep Timer Sleep Timer compare
DMA_T_IOC_0	IO Controller Port 0 I/O pin input transition
DMA_T_IOC_1	IO Controller Port 1 I/O pin input transition
DMA_T_URX0	USART0 USART0 RX complete
DMA_T_UTX0	USART0 USART0 TX complete
DMA_T_URX1	USART1 USART1 RX complete
DMA_T_UTX1	USART1 USART1 TX complete
DMA_T_FLASH	Flash controller Flash data write complete
DMA_T_RADIO	Radio RF packet byte received/transmit
DMA_T_ADC_CHALL	ADC ADC end of a conversion in a sequence, sample ready
DMA_T_ADC_CH11	ADC ADC end of conversion channel 0 in sequence, sample ready
DMA_T_ADC_CH21	ADC ADC end of conversion channel 1 in sequence, sample ready
DMA_T_ADC_CH32	ADC ADC end of conversion channel 2 in sequence, sample ready
DMA_T_ADC_CH42	ADC ADC end of conversion channel 3 in sequence, sample ready
DMA_T_ADC_CH53	ADC ADC end of conversion channel 4 in sequence, sample ready
DMA_T_ADC_CH63	ADC ADC end of conversion channel 5 in sequence, sample ready
DMA_T_ADC_CH74	ADC ADC end of conversion channel 6 in sequence, sample ready
DMA_T_ADC_CH84	ADC ADC end of conversion channel 7 in sequence, sample ready
DMA_T_ENC_DW	AES AES encryption processor requests download input data
DMA_T_ENC_UP	AES AES encryption processor requests upload output data

Definition at line 15 of file dma.h.

enum dma_type_t

transfer types

Enumerator:

DMA_SINGLE	Single
DMA_BLOCK	Block
DMA_RPT	Repeated single
DMA_BLOCK_RPT	Repeated block

Definition at line 74 of file dma.h.

enum dma_vlen_t

variable DMA length modes

Enumerator:

DMA_VLEN_LEN	Use LEN for transfer count
DMA_VLEN_N1	Transfer the number of bytes/words specified by first byte/word + 1 (up to a maximum specified by LEN). Thus transfer count excludes length byte/word.
DMA_VLEN_N	Transfer the number of bytes/words specified by first byte/word (up to a maximum specified by LEN). Thus transfer count includes length byte/word.
DMA_VLEN_N2	Transfer the number of bytes/words specified by first byte/word + 2 (up to a maximum specified by LEN).
DMA_VLEN_N3	Transfer the number of bytes/words specified by first byte/word + 3 (up to a maximum specified by LEN).
DMA_VLEN_RES1	reserved
DMA_VLEN_RES2	reserved
DMA_VLEN_LEN2	Use LEN for transfer count

Definition at line 52 of file dma.h.

---

Function Documentation

void dma_ISR

(

void

)

DMA interrupt service routine.

if callback defined a poll is made to that process

Definition at line 35 of file dma_intr.c.

References process_poll().